GC80960RD66 Intel, GC80960RD66 Datasheet - Page 24

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Intel
Package Information
Table 7.
24
®
i960
®
RX I/O Processor at 3.3 Volts
PCI Signal Descriptions (Sheet 1 of 3)
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, Revision
P_DEVSEL#
P_INT[A:D]#
P_C/BE3:0#
P_FRAME#
P_AD31:0
P_LOCK#
P_PERR#
P_SERR#
2.1 for a more complete definition.
P_IDSEL
P_IRDY#
P_GNT#
P_REQ#
P_RST#
P_PAR
Name
Type
K(Q)
K(Q)
K(Q)
K(Q)
R(Z)
R(Z)
R(Z)
R(Z)
R(Z)
S(L)
R(Z)
R(Z)
S(L)
R(Z)
R(Z)
R(Z)
A(L)
R(Z)
OD
OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
PRIMARY PCI ADDRESS/DATA is the primary multiplexed PCI address and
data bus.
PRIMARY PCI BUS COMMAND and BYTE ENABLE signals are
multiplexed on the same PCI signals. During an address phase,
P_C/BE3:0# define the bus command. During a data phase, P_C/BE3:0#
are used as byte enables.
PRIMARY PCI BUS DEVICE SELECT is driven by a target agent that has
successfully decoded the address. As an input, it indicates whether or not an
agent has been selected.
PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the beginning
and duration of an access on the Primary PCI bus.
PRIMARY PCI BUS GRANT indicates to the agent that access to the bus
has been granted. This is a point-to-point signal.
PRIMARY PCI BUS INITIALIZATION DEVICE SELECT selects the
80960RX during a Configuration Read or Write command on the primary PCI
bus.
PRIMARY PCI BUS INTERRUPT requests an interrupt. The assertion and
deassertion of P_INTx# is asynchronous to S_CLK. A device asserts its
P_INTx# line when requesting attention from its device driver. Once the
P_INTx# signal is asserted, it remains asserted until the device driver clears
the pending request. P_INTx# Interrupts are level sensitive.
PRIMARY PCI BUS INITIATOR READY indicates the initiating agent's (bus
master's) ability to complete the current data phase of the transaction.
PRIMARY PCI BUS LOCK indicates an atomic operation that may require
multiple transactions to complete.
PRIMARY PCI BUS PARITY. This signal ensures even parity across
P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal.
PRIMARY PCI BUS PARITY ERROR is used for reporting data parity errors
during all PCI transactions except a special cycle.
PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent
desires use of the bus. This is a point to point signal.
PRIMARY RESET brings 80960RX to a consistent state. When P_RST# is
asserted:
P_RST# may be asynchronous to S_CLK when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
PRIMARY PCI BUS SYSTEM ERROR reports address and data parity
errors on the special cycle command, or any other system error where the
result would be catastrophic.
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• open drain signals such as P_SERR# are floated.
• S_RST# asserts.
Description
1
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