ICS9248AG-92 IDT, Integrated Device Technology Inc, ICS9248AG-92 Datasheet - Page 9

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ICS9248AG-92

Manufacturer Part Number
ICS9248AG-92
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet

Specifications of ICS9248AG-92

Number Of Elements
2
Supply Current
180mA
Pll Input Freq (min)
14.318MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSSOP
Output Frequency Range
24 to 100MHz
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant

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PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-92. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-92 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
IDT
ICS9248-92
Mobile Pentium II
TM
Mobile Pentium II
TM
TM
System Clock Chip
System Clock Chip
9
309—01/25/10

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