ICS9248AG-92 IDT, Integrated Device Technology Inc, ICS9248AG-92 Datasheet - Page 7

• Manufacturer Part Number: ICS9248AG-92
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of ICS9248AG-92

• Number Of Elements: 2
• Supply Current: 180mA
• Pll Input Freq (min): 14.318MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 24 to 100MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

Power Management
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and
power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board
routing and signal loading may have a large impact on the initial clock distortion also.
Power Management Requirements
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF will be stopped independant of these.
IDT
ICS9248-92
Mobile Pentium II
TM
Mobile Pentium II
TM
TM
System Clock Chip
System Clock Chip
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309—01/25/10