ICS9248AG-92 IDT, Integrated Device Technology Inc, ICS9248AG-92 Datasheet - Page 4

• Manufacturer Part Number: ICS9248AG-92
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of ICS9248AG-92

• Number Of Elements: 2
• Supply Current: 180mA
• Pll Input Freq (min): 14.318MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 24 to 100MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

1.
2.
3.
4.
5.
6.
IDT
Notes:
ICS9248-92
Mobile Pentium II
TM
Dummy Command Code
Mobile Pentium II
Dummy Byte Count
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
• ICS clock will acknowledge each byte one at a
time .
• Controller (host) sends a Stop bit
Controller (Host)
The ICS clock generator is a slave/receiver, I
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
through byte 5
Address
Start Bit
Stop Bit
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
D2
(H )
How to Write:
TM
TM
System Clock Chip
System Clock Chip
For more information, contact IDT for an I
The information in this section assumes familiarity with I
ICS (Slave/Receiver)
General I
2
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
2
C serial interface information
2
C component. It can read back the data stored in the latches for
(H)
4
2
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
C programming application note.
Controller (Host)
Address
Start Bit
Stop Bit
D3
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
(H )
How to Read:
2
C programming.
ICS (Slave/Receiver)
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
309—01/25/10
(H)