W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet - Page 64

• Manufacturer Part Number: W77C32F-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W77C32F-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Framing Error Detection
A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data
communication. Typically the frame error is due to noise and contention on the serial communication
line. The W77C32 has the facility to detect such framing errors and set a flag which can be checked
by software.
The Frame Error FE(FE_1) bit is located in SCON.7(SCON1.7). This bit is normally used as SM0 in
the standard 8051 family. However, in the W77C32 it serves a dual function and is called SM0/FE
(SM0_1/FE_1). There are actually two separate flags, one for SM0 and the other for FE. The flag that
is actually accessed as SCON.7(SCON1.7) is determined by SMOD0 (PCON.6) bit. When SMOD0 is
set to 1, then the FE flag is indicated in SM0/FE. When SMOD0 is set to 0, then the SM0 flag is
indicated in SM0/FE.
The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while
reading or writing to FE or FE_1. If FE is set, then any following frames received without any error will
not clear the FE flag. The clearing has to be done by software.
Multiprocessor Communications
Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the W77C32, the
RI flag is set only if the received byte corresponds to the Given or Broadcast address. This hardware
feature eliminates the software overhead required in checking every received address, and greatly
simplifies the software programmer task.
In the multiprocessor communication mode, the address bytes are distinguished from the data bytes
by transmitting the address with the 9th bit set high. When the master processor wants to transmit a
(SMOD_1)
SMOD=
Overflow
RCLK
TCLK
Timer 1
÷2
RXD
0
SAMPLE
0
0
1
(for Serial Port 0 only)
1
1
DETECTOR
Timer 2 Overflow
1-TO-0
÷16
÷16
Write to
SBUF
START
RX CLOCK
TX CLOCK
TX START
CONTROLLER
DETECTOR
RX
SERIAL
Figure 23: Serial Port Mode 3
BIT
Data Bus
RX SHIFT
TX SHIFT
Internal
LOAD
SBUF
- 64 -
TI
RI
TB8
Receive Shift Register
CLOCK
SIN
PAROUT
Transmit Shift Register
STOP
CLOCK
START
LOAD
PARIN
D8
D8
W77C32/W77C032
SOUT
SBUF
RB8
Serial Port
SBUF
Interrupt
Read
TXD
Internal
Data
Bus