W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet - Page 49

• Manufacturer Part Number: W77C32F-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W77C32F-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

12.2 Priority Level Structure
There are two priority levels for the interrupts, high and low. The interrupt source can be individually
set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower
priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts themselves.
This hierarchy comes into play when the interrupt controller has to resolve simultaneous requests
having the same priority level. This hierarchy is defined as shown below; the interrupts are numbered
starting from the highest priority to the lowest.
Table 7. Priority structure of interrupts
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt
flag is active in one cycle but not responded to, and is not active when the above conditions are met,
the denied interrupt will not be serviced. This means that active interrupts are not remembered; every
polling cycle is new.
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Timer 2 Overflow
Serial Port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Timer
SOURCE
TF2 + EXF2
- 49 -
RI_1 + TI_1
RI + TI
FLAG
WDIF
TF0
TF1
IE0
IE1
IE2
IE3
IE4
IE5
Publication Release Date: December 20, 2005
W77C32/W77C032
PRIORITY LEVEL
12 (lowest)
1 (highest)
10
11
3
5
7
8
9
2
4
6
Revision A5