W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet - Page 23

• Manufacturer Part Number: W77C32F-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W77C32F-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Status Register
HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority
LIP:
XTUP: Crystal Oscillator Warm-up Status. when set, this bit indicates CPU has detected clock to be
SPTA1: Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting data.
SPRA1: Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a data. It
SPTA0: Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting data.
SPRA0: Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It
Timed Access
TA:
Timer 2 Control
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority
interrupt. This bit will be cleared when the program executes the corresponding RETI
instruction.
The Timed Access register controls the access to protected bits. To access protected bits, the
user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.
Now a window is opened in the protected bits for three machine cycles, during which the user
can write to these bits.
ready. Each time the crystal oscillator is restarted by exit from power down mode or the
XTOFF bit is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When
this bit is cleared, it prevents software from setting the XT/ RG bit to enable CPU operation
from crystal oscillator.
It is cleared when TI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0,
CD1 will be ignored when this bit is set to 1 and SWB = 1.
Bit:
is cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0,
CD1 will be ignored when this bit is set to 1 and SWB = 1.
It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1
will be ignored when this bit is set to 1 and SWB = 1.
is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1
will be ignored when this bit is set to 1 and SWB = 1.
Mnemonic: STATUS
Mnemonic: T2CON
Bit:
Mnemonic: TA
7
-
Bit:
TF2
7
HIP
6
TA.7
EXF2
7
6
LIP
5
TA.6
6
RCLK
5
XTUP
4
TA.5
5
TCLK
- 23 -
4
SPTA1
3
TA.4
4
EXEN2
Publication Release Date: December 20, 2005
3
SPRA1
TA.3
2
3
W77C32/W77C032
TR2
2
Address: C7h
SPTA0
TA.2
Address: C5h
Address: C8h
2
1
C/ T2
1
TA.1
SPRA0
1
0
CP/ RL2
Revision A5
0
TA.0
0