ADSP-2171KST-133 Analog Devices Inc, ADSP-2171KST-133 Datasheet - Page 35

• Manufacturer Part Number: ADSP-2171KST-133
• Manufacturer: Analog Devices Inc

Specifications of ADSP-2171KST-133

• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 33.33MHz
• Mips: 33
• Device Input Clock Speed: 33.33MHz
• Ram Size: 10KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

REV. A
ADSP-2173
Parameter
Bus Request/Grant
Timing Requirement:
t
t
Switching Characteristic:
t
t
t
t
t
t
NOTES
1
2
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to DMS, PMS, BMS,
RD, WR Disable
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS, BMS,
RD, WR Enable
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
DMS, PMS, BMS, RD, WR
Disable to BGH Low
BGH High to DMS, PMS, BMS,
RD, WR Enable
PMS, DMS
BMS, RD
CLKOUT
CLKOUT
BGH
BR
WR
BG
2
2
t
Figure 26. Bus Request–Bus Grant
SD
t
1
BH
1
t
t
BS
t
SDB
SDBH
–35–
ADSP-2171/ADSP-2172/ADSP-2173
Min
0.25t
0.25t
0
0
0.25t
0
0
CK
CK
CK
+ 2
+ 22
– 10
t
SE
t
SEC
t
SEH
Max
0.25t
CK
+ 16
Unit
ns
ns
ns
ns
ns
ns
ns
ns