ADSP-2171KST-133 Analog Devices Inc, ADSP-2171KST-133 Datasheet - Page 14

ADSP-2171KST-133

Manufacturer Part Number
ADSP-2171KST-133
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADSP-2171KST-133

Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
33.33MHz
Mips
33
Device Input Clock Speed
33.33MHz
Ram Size
10KB
Program Memory Size
24KB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
128
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
ADSP-2171/ADSP-2172/ADSP-2173
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
(disable XTAL pin when no external
Powerup Context Reset Enable
1 = soft reset (context clear),
HIP Data Registers
1 = disabled, 0 = enabled
4096 Cycle Delay Enable
XTAL Pin Drive Disable
1 = delay, 0 = no delay
Serial Clock Divide Modulus
0 = resume execution
during Powerdown
crystal connected)
HDR2
HDR0
HDR3
HDR1
Powerdown Force
HDR5
HDR4
SPORT1 SCLKDIV
XTALDELAY
9
PDFORCE
0x3FF1
XTALDIS
8
PUCR
7
0x3FE3
0x3FE2
0x3FE1
0x3FE0
0x3FE5
0x3FE4
6
15 14 13 12 11 10
0
5
0
4
0
3
Host HDR5
Host HDR4
Host HDR3
Host HDR2
Host HDR1
Host HDR0
SPORT1 Autobuffer Control Register
0
2
Read
Read
Read
Read
Read
Read
Control Registers
1
15 14 13 12 11 10
0
0
0
–14–
9
0
0x3FEF
8
0
Interrupt Enables
1 = Enable
0 = Disable
15 14 13 12 11 10
7
0
6
0
HMASK Register
9
0
5
0x3FE8
Receive Frame Sync Divide Modulus
8
0
4
7
0
3
6
0
2
SPORT1 RFSDIV
9
5
0
0
1
8
0x3FF0
4
0
0
0
7
3
0
RBUF
Receive Autobuffer Enable
TBUF
Transmit Autobuffer Enable
RMREG
Receive M Register
RIREG
Receive I Register
TMREG
Transmit M Register
TIREG
Transmit I Register
2
0
6
1
0
5
0
0
4
3
Host HDR0
Write
Host HDR1
Write
Host HDR2
Write
Host HDR3
Write
Host HDR4
Write
Host HDR5
Write
2
REV. A
1
0

Related parts for ADSP-2171KST-133