IDT82V3002APV IDT, Integrated Device Technology Inc, IDT82V3002APV Datasheet - Page 12

• Manufacturer Part Number: IDT82V3002APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3002APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

corresponds to the worst case of 18 frame (125 µs per frame) slips in 24
hours. This meets AT&T TR62411 and Telcordia GR-1244-CORE
Stratum 3 requirement of ±0.37 ppm (255 frame slips per 24 hours).
IDT82V3002A goes into Holdover Mode.
3.1.4
required, or a system is just powered up and the network
synchronization has not been achieved.
synchronization signals which are based on the master clock frequency
(OSCi) only and not synchronized to the input reference signal.
master clock (OSCi). So if a ±32 ppm output clock is required, the
master clock must also be ±32 ppm. Refer to
information.
Freerun Mode.
3.2
shown in
three frequencies is selected. Note that both the reference inputs Fref0
and Fref1 must have the same frequency applied to them. Every time
the frequency is changed, the device must be reset to make the change
effective.
Table - 3 Input Reference Frequency Selection
3.3
signals, Fref0 and Fref1, and operates on their falling edges. The
reference is selected by the IN_sel pin, as shown in
selected reference signal is sent to the TIE control block, Reference
Input Monitor and Invalid Input Signal Detection block to be further
processed.
FUNCTIONAL DESCRIPTION
IDT82V3002A
The HOLDOVER pin will be set to logic high whenever the
Freerun Mode is typically used when a master clock source is
In Freerun Mode, the IDT82V3002A provides timing and
The accuracy of the output clock is equal to the accuracy of the
The FREERUN pin will go high whenever the IDT82V3002A works in
The input reference can be 8 kHz, 1.544 MHz or 2.048 MHz. As
The IDT82V3002A accepts two simultaneous reference input
F_sel1
0
0
1
1
Table -
FREERUN MODE
FREQUENCY SELECT CIRCUIT
REFERENCE INPUT SWITCH
3, the F_sel1 and F_sel0 pins determine which of the
F_sel0
0
1
0
1
Input Frequency
1.544 MHz
2.048 MHz
Reserved
8 kHz
"OSC"
Table -
for more
4. The
12
Table - 4 Reference Input Switch Control
will automatically switch to the Short Time Holdover Mode (S4) with the
TIE Control Block disabled. At the S4 stage, if no transient occurs on the
IN_sel pin, the reference signal will be changed from one to the other
and the device will switch back to Normal Mode (S1) automatically.
During the change from S4 to S1, the TIE Control Block can be manually
enabled or disabled. See
3.4
be able to reject the references that are off the nominal frequency by
more than ±12 ppm. The IDT82V3002A monitors the TIE Control Block
input frequency and outputs a signal on the MON_out pin to indicate the
result. Whenever the reference is off the nominal frequency by more
than ±12 ppm, the MON_out pin will go high. The MON_out signal is
updated every 2 seconds.
3.5
IDT82V3002A. The IDT82V3002A will automatically enter Holdover
Mode (Auto-Holdover) if the incoming reference signal is out of the
capture range (See
reference, or a large frequency shift in the input reference. When the
input reference returns to normal, the DPLL will return to Normal Mode.
In Holdover Mode, the output signal of the IDT82V3002A is based on
the output signal 30 ms to 60 ms prior to entering Holdover Mode. The
amount of phase drift in Holdover Mode is negligible because Holdover
Mode is very accurate (e.g., 0.025 ppm). Consequently, the phase delay
between the input and output after switching back to Normal Mode is
preserved.
3.6
use the other reference or the one generated by the storage techniques
instead. But when switching the reference, a step change in phase on
the input reference will occur. And a step change in phase at the input of
the DPLL would lead to unacceptable phase changes in the output
signals. The TIE control block, when enabled, prevents a step change in
phase on the input reference signals from causing a step change in
phase at the output of the DPLL block.
Block diagram.
When a transient voltage occurs at the IN_sel pin, the IDT82V3002A
Telcordia GR-1244-CORE standard recommends that a DPLL should
This circuit monitors the input reference signal into the
If the current reference is badly damaged or lost, it is necessary to
IN_sel
REFERENCE INPUT MONITOR
INVALID INPUT SIGNAL DETECTION
TIE CONTROL BLOCK
0
1
WAN PLL WITH DUAL REFERENCE INPUT
Table -
Figure - 4
8), including a complete loss of input
for details.
Figure - 5
Input Reference
Fref0
Fref1
shows the TIE Control
October 15, 2008