LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 24
LAXP2-17E-5QN208E
Manufacturer Part Number
LAXP2-17E-5QN208E
Description
IC FPGA AUTO 17K LUTS 208-PQFP
Manufacturer
Lattice
Datasheet
1.LAXP2-5E-5TN144E.pdf
(83 pages)
Specifications of LAXP2-17E-5QN208E
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Part Number:
LAXP2-17E-5QN208E
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MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in LA-LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available.
The over• ow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element.
Figure 2-21. MAC sysDSP
Multiplicand
Multiplier
Signed A
Signed B
Addn
Accumsload
Serial Register B in
n
Input Data
Register B
n
n
SROB
n
Register
Register
Register
Register
Input
Input
Input
Input
m
Input Data
Register A
m
n
SROA
Serial Register A in
m
Register
Register
Register
Register
Pipeline
Pipeline
Pipeline
Pipeline
m
n
2-21
To Accumulator
To Accumulator
To Accumulator
To Accumulator
Multiplier
Register
Pipeline
x
(default)
m+n
Accumulator
LA-LatticeXP2 Family Data Sheet
CLK (CLK0,CLK1,CLK2,CLK3)
RST(RST0,RST1,RST2,RST3)
CE (CE0,CE1,CE2,CE3)
m+n+16
(default)
Preload
(default)
m+n+16
Architecture
Output
Overflow
signal
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