LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 17

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Slice Clock Selection
Figure 2-13 shows the clock selections and Figure 2-14 shows the control selections for Slice 0 through Slice 2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals, via routing,
can be used as clock inputs to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-13. Slice 0 through Slice 2 Clock Selection
Figure 2-14. Slice 0 through Slice 2 Control Selection
Edge Clock Routing
LA-LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implemen-
tation of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes
for these clocks.
Secondary Clock
Secondary Clock
Primary Clock
Routing
Routing
Vcc
Vcc
12
12
8
4
1
3
1
2-14
25:1
16:1
LA-LatticeXP2 Family Data Sheet
Clock to Slice
Slice Control
Architecture