NOIL2SC1300A-GDC ON Semiconductor, NOIL2SC1300A-GDC Datasheet - Page 9

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NOIL2SC1300A-GDC

Manufacturer Part Number
NOIL2SC1300A-GDC
Description
LUPA1300-2 COLOR PGA168
Manufacturer
ON Semiconductor
Datasheet

Specifications of NOIL2SC1300A-GDC

Lead Free Status / Rohs Status
Supplier Unconfirmed
Image Sensor Core
sensor consists of a pixel array, analog front end, data block,
and LVDS transmitters and receivers. Separate modules for
the SPI, clock division, and sequencer are also integrated.
The image sensor of 1280 x 1024 active pixels is read out in
progressive scan.
The 6T Pixel
sensitivity and good parasitic light sensitivity (PLS),
implement the pixel architecture shown in Figure 6. This
pixel architecture is designed with a 14 mm x 14 mm pixel
pitch to meet the specifications listed in Table 1 and Table 2
on page 3. This architecture also enables pipelined or
triggered mode.
The floor plan of the architecture is shown in Figure 5. The
To obtain the global shutter feature combined with a high
24x 10-bit digital channels
12x 10-bit digital channels
24 analog channels
Figure 5. Floor Plan of the Sensor
12x LVDS outputs at 630 Msps
SENSOR ARCHITECTURE
Analog front end
LVDS TX and RX
1280 x 1024
Image core
Local register
Data block
http://onsemi.com
9
31.5 Msps
31.5 Msps
63 Msps
x-direction in steps of 24 pixels, and in the y-direction in
steps of one pixel. The starting point of the address can be
uploaded by the SPI.
when the data is multiplexed and prepared for the LVDS
interface.
This architecture enables programmable addressing in the
The AFE prepares the signal for the digital data block
Clk X & Clk Y
Reset
31.5 MHz
Figure 6. 6T Pixel Architecture
63 MHz
Vpix
315 MHz
Sequencer
Divider
Clock
Logic
SPI
&
Clk out
Clk in
Sample
Vmem
Select

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