NOIL2SC1300A-GDC ON Semiconductor, NOIL2SC1300A-GDC Datasheet - Page 16

• Manufacturer Part Number: NOIL2SC1300A-GDC
• Description: LUPA1300-2 COLOR PGA168
• Manufacturer: ON Semiconductor

Specifications of NOIL2SC1300A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Block
end (output stage + ADCs) and the LVDS interface. It muxes
the outputs of 2 ADCs to one LVDS block and performs
some minor data handling:
•
•
The most important registers in this block are:
registers insert a training pattern in the LVDS channels to
sync the LVDS receivers.
(with X=0 to 12) are registers that allow you to enable or
disable the FPN correction (DatachannelX_1[1]), and
generate a test pattern if necessary (datachannelX_1[5:4]
and datachannelX_2[7:0]).
Sequencer Block
disabling image sensor features that are driven by the
onboard sequencer. This block consists of the following
registers:
subregisters:
be ‘1’ during image acquisition.
generated on-chip.
generated through the int_time1, int_time2, and int_time3
pins.
(1) mode.
scheme used when subsampling is enabled.
integration.
integration.
subregisters:
The data block is positioned in between the analog front
Dataconfig. The dataconfig1[7:6] and dataconfig2[7:0]
Datachannels. DatachannelX_1 and DatachannelX_2
The sequencer block group registers allow enabling or
Seqmode1. The seqmode1 registers have the following
Seqmode1[0]: Enables sequencer for image capture, must
Seqmode1[1]: This subregister has two modes:
‘1’: In this default mode the integration timing is
‘0’: In this slave mode, the integration timing must be
Seqmode1[2]: This bit enables pipelined (0) or triggered
Seqmode1[3]: Enable (1) or disable (0) subsampling.
Seqmode1[4]: This bit sets the type of subsampling
‘1’: Color (1:1:0:0:1:1:0:0:1…)
‘0’: Black and White (1:0:1:0:1)
Seqmode1[5]: This bit enables or disables the dual slope
Seqmode1[6]: This bit enables or disables the triple slope
Seqmode2. The seqmode2 register consists of only two
CRC calculation and insertion.
All data can be protected by a 10-bit checksum. The
CRC10 is calculated over all pixels between a Line
Start and a Line End. It is inserted in the data stream
after the line is completed, if input seq_data_crc is
enabled.The polynomial used is
(x^10+x^9+x^6+x^3+x^2+x+1) and 10 bits are
calculated in parallel. When a new line is started, the
seed is the first pixel value of a line. No CRC is
calculated for that value. From then on, every incoming
pixel is updated through the regular CRC.
Training and test pattern generation
http://onsemi.com
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this must be overwritten with the new value ’10001’
immediately after startup.
windows:
following subregisters:
generation on the data and sync channels
correction
of frames grabbed in nondestructive readout mode.
settings (only for those that have ‘granularity selectable’ in
the description). As a result, all timer settings are set either
in number of applied clock cycles, or in the number of
‘readout lines’.
2**seqmode4 [3:0])
outside of ROT to be delayed to the next ROT to avoid image
artifacts.
for the timers when working in clock cycle mode.
digital test pins (monitor1, monitor2, and monitor3 pins)
out.
out.
start address for window 1 (default window).
for window 1 (default window).
address for window 1 (default window).
kernels or X width to be read out for window 1 (default
window).
Seqmode2[4:0]: Default value after startup is ’10000’, but
Seqmode3[6:5]: These two bits set the number of active
‘00’: 1 window
‘01’: 2 windows
‘10’: 3 windows
‘11’: 4 windows (max)
Seqmode3. The seqmode3 register consists of the
Seqmode3[0]: This bit enables or disables the CRC10
Seqmode3[1]: Not applicable
Seqmode3[2]: Enables or disables column FPN
Seqmode3[5:3]: Enables or disables, and sets the number
‘000’: Invalid
‘001’: Default, 1 reset, 1 sample
‘010’: 1reset, 2 samples
‘011’: 1 reset, 3 samples
Seqmode3[6]: Controls the granularity of the timer
‘0’: expressed in number of lines
‘1’: expressed in clock cycles (multiplied by
Seqmode3[7]: Allows syncing of events that happen
Seqmode4. This register consists of four subregisters:
Seqmode4[3:0]: Multiplier factor (2**seqmode4[3:0])
Seqmode4[5:4]: Selects the source signals to be put on the
“00”: integration time settings
“01”: EOS signals
“10”: frame sync signals
“11”: functional test mode
Seqmode4[6]: Enables (1) and disables (0) reverse X read
Seqmode4[7]: Enables (1) and disables (0) reverse Y read
Y1_start (60 and 61, 10 bit). These registers set the Y
X1_start (61, 6bit). This register sets the X start address
Y1_end (62 and 63, 10 bit). These registers set the Y end
X1_kernels (63, 6 bit). This register sets the number of