NOIL2SC1300A-GDC ON Semiconductor, NOIL2SC1300A-GDC Datasheet - Page 17

• Manufacturer Part Number: NOIL2SC1300A-GDC
• Description: LUPA1300-2 COLOR PGA168
• Manufacturer: ON Semiconductor

Specifications of NOIL2SC1300A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

start address for window 2 (if enabled).
for window 2 (if enabled).
address for window 2 (if enabled).
kernels or X width to be read out for window 2 (if enabled).
start address for window 3 (if enabled).
for window 3 (if enabled).
address for window 3 (if enabled).
kernels or X width to be read out for window 3 (if enabled).
start address for window 4 (if enabled).
for window 4 (if enabled).
address for window 4 (if enabled).
kernels or X width to be read out for window 4 (if enabled).
the internal pixel array reset (how long are all pixel reset
simultaneously). This value is expressed in ’number of
lines’ or in clock cycles (depends on seqmode3[6]).
internal dual and triple slope reset pulses when enabled. This
value is expressed in ’number of lines’ or in clock cycles
(depends on seqmode3[6]).
the integration time. This value is expressed in ’number of
lines’ or in clock cycles (depends on seqmode3[6]).
of the dual slope integration time. This value is expressed in
’number of lines’ or in clock cycles (depends on
seqmode3[6]).
A is transferred from the shift register to the active register
bank (that is, sampled) on a rising edge of cs_n. Only the
Y2_start (64 and 65, 10 bit). These registers set the Y
X2_start (65, 6bit). This register sets the X start address
Y2_end (66 and 67, 10 bit). These registers set the Y end
X2_kernels (67, 6 bit). This register sets the number of
Y3_start (68 and 69, 10 bit). These registers set the Y
X3_start (69, 6bit). This register sets the X start address
Y3_end (70 and 71, 10 bit). These registers set the Y end
X3_kernels (71, 6 bit). This register sets the number of
Y4_start (72 and 73, 10 bit). These registers set the Y
X4_start (73, 6bit). This register sets the X start address
Y4_end (74 and 75, 10 bit). These registers set the Y end
X4_kernels (75, 6 bit). This register sets the number of
Res_length (76 and 77). This register sets the length of
Res_dsts_length. This register sets the length of the
Tint_timer (79 and 80). This register sets the length of
Tint_ds_timer (81 and 82). This register sets the length
The ‘out’ line is held to High Z. The data for the address
Figure 10. Read Access (C = ‘0’)
Figure 9. Write Access (C = ‘1’)
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of the triple slope integration time. This value is expressed
in ’number of lines’ or in clock cycles (depends on
seqmode3[6]).
Serial Peripheral Interface (SPI)
output to shift the data in or out the register buffer. The chip’s
configuration registers are accessed from the outside world
through the SPI protocol. A 4-wire bus runs over the chip
and connects the SPI I/Os with the internal register blocks.
To upload the sensor, follow this sequence:
Enable Sequencer
on all the channels, including the sync. The interface
consists of:
•
•
•
•
SPI Protocol
•
•
•
when a read request is performed.
clock, and sampled on the rising edge, as seen in Figure 9 and
Figure 10. This is valid for both the ’in’ and ’out’ bus. The
system clock must be active to keep the SPI uploads stored
on the chip. The SPI clock speed must be slower by a factor
of 30 when compared to the system clock (315 MHz nominal
speed).
register block with address A can write its data on the ‘out’
bus. The data on ‘in’ is ignored.
Tint_ts_timer (83 and 84). This register sets the length
The serial 4-wire interface (or SPI) uses a serial input or
Disable Sequencer ® Upload Sensor for new setting ®
When sequencer is disabled, the training pattern appears
The information on the data ‘in’ line is:
The data ’out’ line is generally in High Z mode, except
Data is always written on the bus on the falling edge of the
cs_n: chip select, when LOW the chip is selected
clk: the spi clock
in: Master out, Slave in, the serial input of the register
out: Master in, Slave out, the serial output of the
register
A command bit C, indicating a write (‘1’) or a read
(‘0’) access
7-bit address
8-bit data word (in case of a write access)