AD9887KS-140 Analog Devices Inc, AD9887KS-140 Datasheet - Page 35

• Manufacturer Part Number: AD9887KS-140
• Description: IC INTRFACE ANALOG/DVI 160-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9887KS-140

• Rohs Status: RoHS non-compliant
• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount

DIGITAL CONTROL
13
CONTROL BITS
14
14
14
15
Table XLVII. HSYNC Input Polarity Override Settings
7:0 Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many pixel clock pulses the sync
separator must count to before toggling high or low. It
works like a low-pass filter to ignore Hsync pulses in order
to extract the Vsync signal. This register should be set to
some number greater than the maximum Hsync pulsewidth.
The default for this register is 32.
2 Scan Enable
This register is used to enable the scan function. When
enabled, data can be loaded into the AD9887 outputs
serially with the scan function. The scan function utilizes
three pins (SCAN
pins are described in Table I.
Scan Enable
0
1
The default for scan enable is 0 (disabled).
1 Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into
the PLL.
Override Bit
0
1
The default for coast polarity override is 0 (polarity
determined by chip).
0 HSYNC Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the Hsync signal going into
the PLL.
Override Bit
0
1
The default for Hsync polarity override is 0 (polarity
determined by chip).
7 HSYNC Input Polarity Status
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the polarity
of the Hsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
Table XLVI. Coast Input Polarity Override Settings
Table XLV. Scan Enable Settings
IN
Scan Function Disabled
Scan Function Enabled
Result
Result
Coast Polarity Determined by Chip
Coast Polarity Determined by User
, SCAN
Result
Hsync Polarity Determined by Chip
Hsync Polarity Determined by User
OUT
, and SCAN
CLK
). These
15
15
16
17
18
19
1A
Hsync Polarity
Status
0
1
6 VSYNC Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
Vsync Polarity
Status
0
1
5 Coast Input Polarity Status
This bit reports the status of the coast input polarity
detection circuit. It can be used to determine the polar-
ity of the coast input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
Table L. Detected Coast Input Polarity Status
Coast Polarity
Status
0
1
7–3 Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the
Sync-on-Green slicer to be adjusted. This register adjusts
the comparator threshold in steps of 10 mV. A setting of zero
results in a 330 mV threshold. The setting of 31 results in
a 10 mV threshold.
The default setting is 23 and corresponds to a threshold
value of 70 mV.
7–0 Pre-Coast
This register allows the Coast signal to be applied prior
to the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
7–0 Post-Coast
This register allows the coast signal to be applied follow-
ing to the Vsync signal. This is necessary in cases where
post-equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
7–0 Test Register
Must be set to default.
7–0 Test Register
Must be set to 41H for proper operation.
Table XLVIII. Detected HSYNC Input Polarity Status
Table XLIX. Detected VSYNC Input Polarity Status
Result
Hsync Polarity is Negative.
Hsync Polarity is Positive.
Result
Vsync Polarity is Active Low.
Vsync Polarity is Active High.
Result
Coast Polarity is Negative.
Coast Polarity is Positive.
AD9887