AD9887KS-140 Analog Devices Inc, AD9887KS-140 Datasheet
AD9887KS-140
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AD9887KS-140 Summary of contents
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GENERAL DESCRIPTION The AD9887 offers designers the flexibility of a dual analog and digital interface for flat panel displays (FPDs single chip. Both interfaces are optimized for excellent image quality supporting display resolutions up to ...
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... IV 1000 2.6 VI 0.8 IV –1 2 Binary AD9887KS-140 Min Typ Max Unit 8 Bits ± 0.5 +1.25/–1.0 LSB +1.25/–1.0 LSB ± 0.5 ± 1.4 LSB ± 2.5 LSB Guaranteed 0.5 V p-p 1.0 V p-p 150 ppm/°C µA 1 µ ...
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... AD9887KS-100 Level Min Typ Max IV 3.0 3.3 3.6 IV 2.2 3.3 3.6 IV 3.0 3.3 3.6 V 140 170 258 330 1 AD9887 AD9887KS-140 Min Typ Max Unit 3.0 3.3 3.6 V 2.2 3.3 3.6 V 3.0 3.3 3.6 V 155 215 258 330 MHz dBc °C/W 30 ...
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... L Output Drive = Med Output Drive = Low Output Drive = High LHT L Output Drive = Med Output Drive = Low Output Drive = High Output Drive = Med Output Drive = Low Test AD9887KS Level Min Typ Max Unit 8 Bits GND – GND – 0.8 V ...
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... Exposure to absolute maximum ratings for extended periods may affect device reliability. Model AD9887KS-140 AD9887KS-100 AD9887/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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AD9887 PIN 1 GND 2 IDENTIFIER GREEN A<7> 3 GREEN A<6> 4 GREEN A<5> 5 GREEN A<4> GREEN A<3> GREEN A<2> 8 GREEN A<1> 9 GREEN A<0> GND 12 GREEN B<7> ...
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P in Pin Type Name Function Analog Video R Analog Input for Converter R AIN Inputs G Analog Input for Converter G AIN B Analog Input for Converter B AIN External HSYNC Horizontal SYNC Input Sync/Clock VSYNC Vertical SYNC Input ...
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AD9887 DESCRIPTIONS OF PINS SHARED BETWEEN ANALOG AND DIGITAL INTERFACES HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the video HSYNC. The polarity of this output can be controlled via a serial bus bit. In analog interface mode ...
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Pin Type Pin Name Function Analog Video Inputs R Analog Input for Converter R AIN G Analog Input for Converter G AIN B Analog Input for Converter B AIN External HSYNC Horizontal SYNC Input VSYNC Vertical SYNC Input Sync/Clock SOGIN ...
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AD9887 CLAMP External Clamp Input (Optional) This logic input may be used to define the time during which the input signal is clamped to the reference dc level, (ground for RGB or midscale for YUV). It should be exercised when ...
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Either or both signals may be used, depend- ing on the timing mode and interface design employed. HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and dura- tion of this output can ...
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AD9887 Power Management The AD9887 is a dual interface device with shared outputs. Only one interface can be used at a time. For this reason, the chip automatically powers down the unused interface. When the analog interface is being used, ...
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THEORY OF OPERATION AND DESIGN GUIDE (ANALOG INTERFACE) General Description The AD9887 is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel monitors or projectors. The device is ideal for implementing a ...
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AD9887 clamping on the tip of HSYNC. Fortunately, there is virtually always a period following HSYNC called the back porch where a good black reference is provided. This is the time when clamp- ing should be done. The clamp timing ...
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Sync-on-Green The Sync-on-Green input operates in two steps. First, it sets a baseline clamp level from the incoming video signal with a negative peak detector. Second, it sets the Sync trigger level (nominally 150 mV above the negative peak). The ...
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AD9887 Table V. VCO Frequency Ranges Pixel Clock PV1 PV0 Range (MHz 12– 35– 70–110 1 1 110–140 Table VI. Charge Pump Current/Control Bits Ip2 Ip1 Ip0 ...
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OFFSET 7 DAC IN x1.2 CLAMP V OFF 0.5V V OFF (128 CODES) 0V SCAN Function The SCAN function is intended as a pseudo JTAG function for manufacturing test of the board. The ordinary operation of the AD9887 is disabled ...
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AD9887 ...
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RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA HSOUT RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA HSOUT P0 P1 ...
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AD9887 RGB HSYNC PxCK HS 3-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT RGB HSYNC PxCK HS ADCCK DATACK D OUTA D OUTB HSOUT ...
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RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT RGB IN HSYNC PxCK HS 7-PIPE DELAY ADCCK DATACK D ...
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AD9887 RGBIN HSYNC PXCK HS 6-PIPE DELAY ADCCK DATACK GOUTA ROUTA HSOUT Pin Type Pin Name Digital Video Data Inputs Rx0+ Rx0– Rx1+ Rx1– Rx2+ Rx2– Digital Video Clock Inputs RxC+ RxC– Termination Control R TERM Outputs ...
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DIGITAL INTERFACE PIN DESCRIPTIONS Digital Video Data Inputs Rx0+ Positive Differential Input Video Data (Channel 0) Rx0– Negative Differential Input Video Data (Channel 0) Rx1+ Positive Differential Input Video Data (Channel 1) Rx1– Negative Differential Input Video Data (Channel 1) ...
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AD9887 GENERAL TIMING DIAGRAMS (DIGITAL INTERFACE) 80% 20% D LHT CIP CIP CIH CIH T CIL DIFF DIFF T CCS R X2 DATACK (INTERNAL) ...
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Serial Register Map The AD9887 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Read and ...
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AD9887 Read and Hex Write or Default Address Read Only Bits Value 0FH R/W 7 10H R/W 7 11H RO 7:1 Table IX. Control Register Map (continued) Register Name Function PLL and Bit ...
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Read and Hex Write or Default Address Read Only Bits Value 12H R/W 7 13H 7:0 00100000 R/W 14H R/W 7:0 1 15H RO 7:5 16H 7:2 10111*** R/W ******1* 17H 7:0 00000000 R/W 18H 7:0 ...
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AD9887 Read and Hex Write or Default Address Read Only Bits Value 1BH R/W 7:0 00000000 1CH R/W 7:0 000001** ******1* 1DH RO 7:0 1EH RO 7:0 1FH RO 7:0 NOTE 1 The AD9887 only updates the PLL divide ratio ...
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SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 00 7–0 Chip Revision Bits 7 through 4 represent functional revisions to the analog interface. Changes in these bits will generally indicate that software and/or hardware changes will be required for the chip ...
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AD9887 06 7–0 Clamp Duration An 8-bit register that sets the duration of the internally generated clamp. When EXTCLMP = 0, a clamp signal is generated inter- nally position established by the clamp placement and for a duration ...
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When DEMUX = 0, this bit is ignored as data always comes out of only Port HSYNC Output Polarity One bit that determines the polarity of the HSYNC out- put and the SOG output. Table XV shows ...
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AD9887 A Logic 1 enables the external CKEXT input pin. In this mode, the PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust (PHASE) is still functional. The power-up default value is EXTCLK = Red Clamp ...
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SYNC DETECTION AND CONTROL 11 7 Analog Interface HSYNC Detect This bit is used to indicate when activity is detected on the HSYNC input pin (Pin 82). If HSYNC is held high or low, activity will not be detected. Table ...
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AD9887 Table XXXVI. Active VSYNC Results Bit 5 (VSYNC Detect) Override AVS Bit 2 in 12H AVS = 1 means Sync separator. AVS = 0 means VSYNC input. The override bit is ...
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DIGITAL CONTROL 13 7:0 Sync Separator Threshold This register is used to set the responsiveness of the sync separator. It sets how many pixel clock pulses the sync separator must count to before toggling high or low. It works like ...
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AD9887 1B 7–0 Test Register Must be set to 10H for proper operation. 1C 7–2 Test Bits Must be set to 6FH for proper operation Output Format Mode Select A bit that configures the output data in 4:2:2 ...
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SDA t BUFF t DHO t STAH SCL Write to four consecutive control registers ➥Start signal ➥Slave Address byte (R/W bit = LOW) ➥Base Address byte ➥Data byte to base address ➥Data byte to (base address + 1) ➥Data byte ...
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AD9887 SYNC STRIPPER NEGATIVE PEAK CLAMP SOG HSYNC IN ACTIVITY DETECT COAST VSYNC IN ACTIVITY POLARITY DETECT DETECT PCB LAYOUT RECOMMENDATIONS The AD9887 is a high-performance, high-speed analog device. As such, to get the maximum performance out of the part ...
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It is particularly important to maintain low noise and good stability of PV (the clock generator supply). Abrupt changes can result in similarly abrupt changes in sampling clock D phase and frequency. This can be avoided by ...
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AD9887 0.041 (1.03) 0.035 (0.88) 0.029 (0.73) SEATING 0.004 (0.10) 0.010 (0.25) CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. OUTLINE DIMENSIONS Dimensions shown in inches ...