MT46H8M32LFB5-6:H Micron Technology Inc, MT46H8M32LFB5-6:H Datasheet - Page 21

• Manufacturer Part Number: MT46H8M32LFB5-6:H
• Description: IC SDRAM 256MB 166MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:H

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 7: I
Notes 1–5 apply to all parameters/conditions in this table; V
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Parameter/Condition
Operating 1 bank active precharge current:
t
dress inputs are switching every 2 clock cycles; Data bus inputs
are stable
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH;
switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle CKE =
HIGH; CS = HIGH;
switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle, CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Active power-down standby current: 1 bank active, CKE = LOW;
CS = HIGH;
ing; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1 bank ac-
tive, CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS =
HIGH;
Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank active,
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
Operating burst read: 1 bank active; BL = 4; CL = 3;
(MIN); Continuous READ bursts; I
switching every 2 clock cycles; 50% data changing each burst
Operating burst write: One bank active; BL = 4;
Continuous WRITE bursts; Address inputs are switching; 50% da-
ta changing each burst
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data bus
inputs are stable
Deep power-down current: Address and control pins are stable;
Data bus inputs are stable
CK (MIN); CKE is HIGH; CS is HIGH between valid commands; Ad-
t
CK =
DD
t
CK =
t
CK (MIN); Address and control inputs are switching;
Specifications and Conditions (x32)
t
t
t
CK (MIN); Address and control inputs are switch-
CK =
CK =
t
t
CK (MIN); Address and control inputs are
CK (MIN); Address and control inputs are
OUT
= 0mA; Address inputs are
t
RC =
t
CK =
t
t
t
RFC = 110ns
RFC =
RC (MIN);
t
CK =
t
CK (MIN);
t
REFI
t
CK
DD
21
t
CK =
/V
Electrical Specifications – I
DDQ
256Mb: x16, x32 Mobile LPDDR SDRAM
Symbol
= 1.70–1.95V
I
I
I
I
I
I
I
I
I
I
I
DD2NS
DD3NS
DD2PS
DD3PS
DD4W
I
DD2N
DD3N
DD4R
I
DD5A
I
DD2P
DD3P
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD0
DD5
DD8
300
300
140
125
105
60
15
16
10
-5
8
3
2
7
2
300
300
130
115
105
-54
55
14
15
10
7
3
2
6
2
Max
300
300
115
100
105
© 2008 Micron Technology, Inc. All rights reserved.
50
14
14
10
-6
5
3
2
6
2
DD
-75
300
300
105
40
12
12
95
85
10
5
3
2
6
2
Parameters
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6