PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 63

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. EEPROM INTERFACE
The EEPROM interface consists of five pins: SR_DI (EEPROM data input), SR_DO (EEPROM data
output), SR_CS (EEPROM chip select), SR_CLK_O (EEPROM clock output), and SR_ORG (EEPROM
organization). The device may control a 93C56 or compatible parts using 2K bits. The EEPROM is used to
initialize a number of registers before enumeration. This is accomplished at start-up when RTS[0] is
de-asserted, at which time the data from the EEPROM is loaded. The EEPROM interface is organized into
a 16-bit base, and the device supplies a 7-bit EEPROM word address.
8.1. AUTO MODE EERPOM ACCESS
The device may access the EEPROM in a WORD or BYTE format, which is decided by the SR_ORG# at
start-up. If SR_ORG# is asserted at start-up, EEPROM is accessed using the WORD format. Otherwise,
Byte format is used.
8.2. EEPROM MODE AT RESET
During a reset, the device will automatically load the information/data from the EEPROM if the automatic
load condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized,
and if RTS[0] is de-asserted, the autoload initiates right after the reset.
8.3. EEPROM SPACE ADDRESS MAP AND DESCRIPTION
September 2009 – Revision 1.3
Pericom Semiconductor
EEPROM
ADDRESS
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
PCIE REGISTER OFFSET
Offset 00h bit[15:0]
Offset 00h bit[31:16]
Offset 2Ch bit[15:0]
Offset 2Ch bit[31:16]
Bit[0] - Offset 80h bit[21]
Bit[3:1] - Offset 80h bit[24:22]
Bit[4] - Offset 80h bit[25]
Bit[5] - Offset 80h bit[26]
Bit[10:6] - Offset 80h bit[31:27]
Bit[11] - Offset 84h bit[3]
Bit[13:12] - Offset A8h bit[14:13]
Offset B0h bit[15:0]
Offset B0h bit [31:16]
Bit[1:0] - Offset ECh bit[11:10]
Bit[4:2] - Offset ECh bit[14:12]
Bit[7:5] - Offset ECh bit[17:15]
Offset B4h bit[15:0]
09-0088
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DEFAULT
01000b
A868h
12D8h
7954h
0000h
0000h
0000h
0000h
0000h
Value
111b
011b
000b
00b
11b
0b
1b
1b
1b
DESCRIPTION
Check Code
Vendor ID
Device ID
Subsytem Vendor ID
Subsytem ID
Device Specific Initialization: When set, the DSI is
required.
Aux. Current: When set, the I/O bridge needs 375
mA in D3 state.
D1 Support: When set, this bridge supports D1
Power Management state.
D2 Support: When set, this bridge supports D2
Power Management state.
PME Support: When set, the PME supports D1 and
D2 Power Management states.
No Soft Reset: When set, the device does not
trigger the Internal Reset Command during the
transition from D3hot to D0 power state.
XPIP CSR0
Replay Time-out Counter
Acknowledge Latency Timer
ASPM Capability Support: When set, this bridge
supports L0s and L1 entry
Exit L0s Latency Timer
Exit L1 Latency Timer
UART Transmitter Drive Enable:
RS232/422/485-2W/485-4W Selection for UART 0
to 3
PCI Express® Quad UART
PI7C9X7954
Datasheet