PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 52

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Each register in the UART Register Block can be access by adding an offset to the UART Memory Base
Address. The following table lists the arrangement of the registers in the UART Register Block in memory
mode.
7.2.1.
September 2009 – Revision 1.3
Pericom Semiconductor
RECEIVE HOLDING REGISTER – OFFSET 00h
Table 7-4 Memory-Map mode
Offset
UART Memory Base Address + 00h
UART Memory Base Address + 00h
UART Memory Base Address + 01h
UART Memory Base Address + 02h
UART Memory Base Address + 02h
UART Memory Base Address + 04h
UART Memory Base Address + 04h
UART Memory Base Address + 05h
UART Memory Base Address + 06h
UART Memory Base Address + 07h
UART Memory Base Address + 08h
UART Memory Base Address + 09h
UART Memory Base Address + 0Ah
UART Memory Base Address + 0Bh
UART Memory Base Address + 0Ch
UART Memory Base Address + 0Dh
UART Memory Base Address + 0Eh
UART Memory Base Address + 0Fh
UART Memory Base Address + 10h
UART Memory Base Address + 11h
UART Memory Base Address + 12h
UART Memory Base Address + 13h
UART Memory Base Address + 14h
UART Memory Base Address + 15h
UART Memory Base Address + 16h
UART Memory Base Address + 17h
UART Memory Base Address + 100h
~17Fh
UART Memory Base Address + 180h
~1FFh
BIT
7:0
FUNCTION
Rx Holding
09-0088
RO
TYPE
Page 52 of 70
Register Name
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
Interrupt Status Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Special Function Register
Divisor Latch Low
Divisor Latch High
Enhanced Function Register
XON 1 Character/Special
Character 1
XON 2 Character/Special
Character 2
XOFF 1 Character/Special
Character 3
XOFF 2 Character/Special
Character 3
ACR Register
Transmitter Interrupt Trigger
Level
Receiver Interrupt Trigger Level
Automatic Flow control lower
trigger level
Automatic Flow control lower
higher level
Baud rate Prescale
Receive FIFO Data Counter /
Line Status Register Counter
Transmit FIFO Data Counter /
Sample Clock Register
Global Register of LSR
UART0 FIFO DATA Register.
Use this register to map FIFO
data content.
UART0 FIFO DATA LSR
Register. Use this register to map
FIFO data relative LSR content.
DESCRIPTION
When data are read from the Receive Holding Register (RHR),
they are removed from the top of the receiver’s associated
FIFOs, which holds a queue of data received by the receiver.
Data read from the RHR when the FIFOs are empty are invalid.
The Line Status Register (LSR) indicates the full or empty status
of the FIFOs.
Reset to 00h.
Mnemonic
RFD / LSR
FIFO_LSR
Counter /
FIFO_D
Counter
XOFF1
XOFF2
XON1
XON2
GLSR
MCR
MSR
RHR
THR
LCR
DLL
DLH
ASR
FCH
FCR
LSR
SFR
EFR
TTL
RTL
FCL
CPR
TFD
SCR
IER
ISR
PCI Express® Quad UART
Register Type
WO
RW
WO
RW
RW
RW
WO
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
PI7C9X7954
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