PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 36

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.50. DEVICE CAPABILITIES REGISTER – OFFSET E4h
6.2.51. DEVICE CONTROL REGISTER – OFFSET E8h
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
2:0
4:3
5
8:6
11:9
12
13
14
15
17:16
25:18
27:26
31:28
BIT
0
1
2
FUNCTION
Max_Payload_Size
Supported
Phantom Functions
Supported
Extended Tag Field
Supported
Endpoint L0s
Acceptable Latency
Endpoint L1
Acceptable Latency
Attention Button
Present
Attention Indicator
Present
Power Indicator
Present
Role_Base Error
Reporting
Reserved
Captured Slot Power
Limit Value
Captured Slot Power
Limit Scale
Reserved
FUNCTION
Correctable Error
Reporting Enable
Non-Fatal Error
Reporting Enable
Fatal Error
Reporting Enable
09-0088
TYPE
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
Page 36 of 70
DESCRIPTION
Indicates the maximum payload size that the I/O bridge can support
for TLPs. The I/O bridge supports 128 bytes max payload size.
Reset to000b.
It is not implemented. Hardwired to 00b.
It is not implemented. Hardwired to 0b.
Acceptable total latency that an Endpoint can withstand due to the
transition from L0s state to the L0 state.
Reset to 000b.
Acceptable total latency that an Endpoint can withstand due to the
transition from L1 state to the L0 state.
Reset to 000b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
When set, indicated that the device implements the functionality
originally defined in the Error Reporting ECN. The default value
may be changed by auto-loading from EEPROM.
Reset to 1b.
Reset to 00b.
In combination with the Slot Power Limit Scale value, specifies the
upper limit on power supplied by slot.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00h”.
Reset to 00b.
Specifies the scale used for the Slot Power Limit Value.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00b”.
Reset to 00b.
Reset to 0h.
DESCRIPTION
0b: Disable Correctable Error Reporting.
1b: Enable Correctable Error Reporting.
Reset to 0b.
0b: Disable Non-Fatal Error Reporting.
1b: Enable Non-Fatal Error Reporting.
Reset to 0b.
0b: Disable Fatal Error Reporting.
1b: Enable Fatal Error Reporting.
Reset to 0b.
PCI Express® Quad UART
PI7C9X7954
Datasheet