PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 38

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.54. LINK CONTROL REGISTER – OFFSET F0h
6.2.55. LINK STATUS REGISTER – OFFSET F0h
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
3:0
11:10
14:12
17:15
23:18
31:24
BIT
1:0
2
3
4
5
6
7
15:8
BIT
9:4
FUNCTION
Active State Power
Management
(ASPM) Control
Reserved
Read Completion
Boundary (RCB)
Link Disable
Retrain Link
Common Clock
Configuration
Extended Synch
RsvdP
FUNCTION
Maximum Link
Speed
Maximum Link
Width
Active State Power
Management
(ASPM) Support
L0s Exit Latency
L1 Exit
Latency
Reserved
Port Number
FUNCTION
09-0088
TYPE
TYPE
TYPE
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 38 of 70
DESCRIPTION
Indicates the Maximum Link Speed of the given PCIe Link.
Defined encodings are: 0001b, which indicates 2.5 Gb/s Link
Reset to 1h.
Indicates the maximum width of the given PCIe Link.
Reset to 000001b (x1).
Indicates the level of ASPM supported on the given PCIe Link. The
I/O bridge supports L0s and L1 entry. The default value may be
changed by auto-loading from EEPROM.
Reset to 11b.
Indicates the L0s exit latency for the given PCIe Link. The length of
time this I/O bridge requires to complete transition from L0s to L0 is
in the range of 256ns to less than 512ns. The default value may be
changed by auto-loading from EEPROM.
Reset to 011b.
Indicates the L1 exit latency for the given PCIe Link. The length of
time this I/O bridge requires to complete transition from L1 to L0 is
in the range of 16us to less than 32us. The default value may be
changed by auto-loading from EEPROM.
Reset to 000b.
Reset to 00000b.
It is not implemented. Hardwired to 00h.
DESCRIPTION
00b: ASPM is Disabled.
01b: L0s Entry Enabled.
10b: L1 Entry Enabled.
11b: L0s and L1 Entry Enabled.
Note that the receiver must be capable of entering L0s even when the
field is disabled.
Reset to 00b.
Reset to 0h.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
0b: The components at both ends of a link are operating with
asynchronous reference clock.
1b: The components at both ends of a link are operating with a
distributed common reference clock.
Reset to 0b.
When set, it transmits 4096 FTS ordered sets in the L0s state for
entering L0 state and transmits 1024 TS1 ordered sets in the L1 state
for entering L0 state
Reset to 0b.
Reset to 00h.
DESCRIPTION
PCI Express® Quad UART
PI7C9X7954
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