FIN12ACGFX Fairchild Semiconductor, FIN12ACGFX Datasheet - Page 6
![IC SERIALIZER/DESERIALIZER 42BGA](/photos/6/92/69251/fin12acgfx_sml.jpg)
FIN12ACGFX
Manufacturer Part Number
FIN12ACGFX
Description
IC SERIALIZER/DESERIALIZER 42BGA
Manufacturer
Fairchild Semiconductor
Series
SerDes™r
Datasheet
1.FIN12ACGFX.pdf
(21 pages)
Specifications of FIN12ACGFX
Function
Serializer/Deserializer
Data Rate
560Mbps
Input Type
LVCMOS
Output Type
LVCMOS
Number Of Inputs
12
Number Of Outputs
12
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-30°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
42-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FIN12ACGFXTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FIN12ACGFX
Manufacturer:
VISHAY
Quantity:
3 791
Company:
Part Number:
FIN12ACGFX
Manufacturer:
Fairchild Semiconductor
Quantity:
10 000
FIN12AC Rev. 1.1.2
© 2006 Fairchild Semiconductor Corporation
Serializer Operation Mode
The serializer configurations are described in the follow-
ing sections. The basic serialization circuitry works simi-
larly in these modes, but the actual data and clock
streams differ, dependent on whether CKREF is the
same as the STROBE signal. When it is stated that
CKREF = STROBE, the CKREF and STROBE signals
have an identical frequency of operation, but may or may
not be phase aligned. When it is stated that CKREF does
not equal STROBE, each signal is distinct and CKREF
must be running at a frequency high enough to avoid any
loss of data condition. CKREF must never be a lower fre-
quency than STROBE.
Serializer Operation: Modes, 1, 2, 3 DIRI = 1,
CKREF = STROBE
The PLL must receive a stable CKREF signal to achieve
lock prior to valid data being sent. During PLL stabiliza-
tion phase, STROBE should not be connected to the
CKREF signal.
Once the PLL is stable and locked, the device can begin
to capture and serialize data. Data is captured on the
rising edge of the STROBE signal and serialized. When
operating in serializer mode, the internal deserializer cir-
cuitry is disabled, including the DS input buffer. The
CKSI serial inputs remain active to allow the pass
through of the CKSI signal to the CKP output.
Serializer Operation: DIRI=1, CKREF Does Not
= STROBE
driven to valid levels or left to float. For lowest power
operation, let the CKSI inputs float.If the same signal is
not used for CKREF and STROBE, the CKREF signal
must be run at a higher frequency than the STROBE rate
to serialize the data correctly. The actual serial transfer
rate remains at 14 times the CKREF frequency. A data
value of zero is sent when no valid data is present in the
serial bit stream. The operation of the serializer other-
wise remains the same.
The exact frequency that the reference clock needs is
dependent upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the minimum
frequency of this spread spectrum clock should be used
in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly if the STROBE signal has
significant cycle-to-cycle variation, the maximum cycle-
to-cycle time needs to be factored into the selection of
the CKREF frequency.
If this mode is not needed, the CKSI inputs can either be
6
Serializer Operation: DIRI = 1, No CKREF
A third method of serialization uses a free-running bit
clock on the CKSI signal. This is enabled by grounding
the CKREF signal and driving the DIRI signal HIGH.
At power-up, the device is configured to accept a serial-
ization clock from CKSI. If a CKREF is received, this
device enables the CKREF serialization mode. The
device remains in this mode even if CKREF is stopped.
To re-enable this mode, the device must be powered
down and powered back up with “logic 0” on CKREF.
Deserializer Operation Mode
The operation of the deserializer is dependent on the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device generating the serial data and clock sig-
nals that are inputs to the deserializer.
When operating in derserializer mode, the internal serial-
izer circuitry is disabled, including the parallel data input
buffers. If there is a CKREF signal provided, the CKSO
serial clock continues to transmit bit clocks. When S1
and S2 are asserted low, all CMOS outputs are driven
low at the output of the deserializer.
Deserializer Operation DIRI = 0 (Serializer
Source: CKREF = STROBE
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
serial port and deserializer through use of the bit clock
sent with the data.
Deserializer Operation: PwrDwn = 1, DIRI = 0
(Serializer Source: CKREF Does Not = STROBE)
The logical operation of the deserializer remains the
same if the CKREF is equal in frequency to the STROBE
or at a higher frequency than the STROBE. The actual
serial data stream presented to the deserializer differs
because it has nonvalid data bits sent between words.
The duty cycle of CKP varies based on the ratio of the
frequency of the CKREF signal to the STROBE signal.
The frequency of the CKP signal is equal to the STROBE
frequency. The CKP HIGH time is equal to STROBE
period - half of the CKREF period.
www.fairchildsemi.com