SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 73

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
SAA7114_3
Product data sheet
Fig 34. Output timing I port for serial 8-bit data at start of a line (ICODE = 1)
IPD [ 7:0 ]
IGPH
ICLK
IDQ
00
9.7.1 I port output timing
9.7.2 X port input timing
9.7 Basic input and output timing diagrams I port and X port
FF
Table 34:
[1]
Figure 34
active gate signals. If reference pulses are programmed, these pulses are generated on
the rising edge of the logic 1 active gates. Valid data is accompanied by the output data
qualifier on pin IDQ. In addition invalid cycles are marked with output code 00h.
The IDQ output pin may be defined to be a gated clock output signal
(ICLK AND internal IDQ).
At the X port the input timing requirements are the same as those for the I port output. But
different to those below:
Remark: All timings illustrated in
output stream (no handshake with the external hardware).
Symbol Pin
HPD7 to
HPD0
•
•
•
00
Pin numbers for LQFP100 in parenthesis.
It is not necessary to mark invalid cycles with a 00h code
No constraints on the input qualifier (can be a random pattern)
XCLK may be a gated clock (XCLK AND external XDQ)
00
A13, D12,
C12, B12,
A12, C11,
B11 and A11
(64 to 67 and
69 to 72)
to
Signals dedicated to the host port
Figure 40
[1]
SAV
00
Rev. 03 — 17 January 2006
illustrate the output timing via the I port. IGPH and IGPV are logic 1
I/O
I/O
C
B
Description
16-bit extension for digital I/O (chrominance
component)
Y
Figure 34
C
R
Y
to
Figure 40
00
PAL/NTSC/SECAM video decoder
are given for an uninterrupted
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
C
B
Y
Bit
IPE[1:0] 87h[1:0],
ITRI[8Fh[6]] and
I8_16[93h[6]]
SAA7114
C
R
Y
mhb550
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