SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 63

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
SAA7114_3
Product data sheet
8.6.3 Other control signals
Table 23:
Further control signals are available to define reference clock edges and vertical
references; see
Table 24:
AMXCLK
(MHz)
12.288
11.2896
8.192
Signal
APLL[3Ah[3]]
AMVR[3Ah[2]]
LRPH[3Ah[1]]
SCPH[3Ah[0]]
Programming examples for ASCLK/ALRCLK clock generation
Control signals for reference clock edges and vertical references
ASCLK
(kHz)
1536
768
1411.2
2822.4
1024
2048
Table
Description
Audio PLL mode
Audio Master clock Vertical Reference
ALRCLK phase
ASCLK phase
0 = PLL closed
1 = PLL open
0 = internal V
1 = external V
0 = invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1 = don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
0 = invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1 = don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK
Rev. 03 — 17 January 2006
24.
SDIV
Decimal
3
7
3
1
3
1
Hex
03
07
03
01
03
01
ALRCLK
(kHz)
48
48
44.1
44.1
32
32
PAL/NTSC/SECAM video decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
LRDIV
Decimal
16
8
16
32
16
32
SAA7114
Hex
10
08
10
10
10
10
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