ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 75

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

RESET/STOP MANAGER (Cont’d)
The on-chip Timer/Watchdog generates a reset
condition if the Watchdog mode is enabled
(WCR.WDEN cleared, R252 page 0), and if the
programmed period elapses without the specific
code (AAh, 55h) written to the appropriate register.
The input pin RESET is not driven low by the on-
chip reset generated by the Timer/Watchdog.
When the Reset pin goes high again, a delay occurs
before exiting the Reset state. Subsequently a short
Boot routine is executed from the device internal
Boot ROM, and control then passes to the user pro-
gram.
The Boot routine sets the device characteristics
and loads the correct values in the Memory Man-
agement Unit’s pointer registers, so that these
point to the physical memory areas as mapped in
the specific device. The precise duration of this
short Boot routine varies from device to device,
depending on the Boot ROM contents.
At the end of the Boot routine the Program Coun-
ter will be set to the location specified in the Reset
Vector located in the lowest two bytes of memory.
5.6.1 Reset Pin Timing
To improve the noise immunity of the device, the
Reset pin has a Schmitt trigger input circuit with
hysteresis. In addition, a filter will prevent an un-
wanted reset in case of a single glitch of less than
50 ns on the Reset pin. The device is certain to re-
set if a negative pulse of more than 20µs is ap-
ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
plied. When the reset pin goes high again, a delay
of up to 4µs will elapse before the RCCU detects
this rising front. From this event on, 20478 (about
5 ms with a 4MHz quartz) oscillator clock cycles
(CLOCK1) are counted before exiting the Reset
state (+-1 CLOCK1 period depending on the delay
between the positive edge the RCCU detects and
the first rising edge of CLOCK1)
If the ST9 is a ROMLESS version, without on-chip
program memory, the memory interface ports are
set to external memory mode (i.e Alternate Func-
tion) and the memory accesses are made to exter-
nal Program memory with wait cycles insertion.
Figure 38. Recommended Signal to be Applied
on Reset Pin
0.7 V
V
0.3 V
RESET
V
CC
CC
CC
Minimum
20 µs
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