ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 104

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
7.3.3.5 Forced Compare Mode
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
When the FOLV i bit is set, the OLVL i bit is copied
to the OCMP i pin. The OLVL i bit has to be toggled
in order to toggle the OCMP i pin when it is enabled
(OC i E bit=1).
The OCF i bit is not set, and thus no interrupt re-
quest is generated.
7.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
– Select the edge of the active transition on the
And select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedi-
– Set the OPM bit.
– Select the timer clock CC[1:0] (see
Figure 61.
104/179
plied to the OCMP1 pin after the pulse.
plied to the OCMP1 pin during the pulse.
ICAP1 pin with the IEDG1 bit .
cated to the Output Compare 1 function.
Clock Control
9
COUNTER
One
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
OCMP1
ICAP1
FOLV2 FOLV1 OLVL2
Bits).
Pulse Mode Timing
....
FFFC FFFD FFFE
Table 22
OLVL2
OLVL1
Load the OC1R register with the value corre-
sponding to the length of the pulse (see the formu-
la in Section 7.3.3.7).
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OC1R
register, the OLVL1 bit is output on the OCMP1
pin, (See
Note: The OCF1 bit cannot be set by hardware in
one pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is set.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
compare1
2ED0 2ED1 2ED2
event occurs
on ICAP1
Counter
= OC1R
When
Figure
When
OLVL1
61).
2ED3
One pulse mode cycle
OCMP1 = OLVL2
OCMP1 = OLVL1
FFFC FFFD
Counter is
initialized
to FFFCh
OLVL2