ST92T141K4M6 STMicroelectronics, ST92T141K4M6 Datasheet - Page 102

• Manufacturer Part Number: ST92T141K4M6
• Description: Microcontrollers (MCU) OTP EPROM 16K SPI
• Manufacturer: STMicroelectronics

Specifications of ST92T141K4M6

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 16 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-34
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / Rohs Status: No

ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
7.3.3.4 Output Compare
In this section, the index, i , may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
Timing resolution is one count of the free running
counter: (
Procedure
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OC i E bit if an output is needed then the
– Select the timer clock CC[1:0] (see
And select the following in the CR1 register:
– Select the OLVL i bit to applied to the OCMP i pins
– Set the OCIE and OCIS bits (or EFTIS bit if only
When match is found:
– OCF i bit is set.
– The OCMP i pin takes OLVL i bit value (OCMP i
102/179
OCMP i pin is dedicated to the output compare i
function.
Clock Control
after the match occurs.
global interrupt is available) to generate an inter-
rupt if it is needed.
pin latch is forced low during reset and stays low
until valid compares change it to OLVL i level).
– Assigns pins with a programmable value if the
– Sets a flag in the status register
– Generates an interrupt if enabled
9
OC i R
OC i E bit is set
INTCLK /
Bits).
i
R value to 8000h.
CC[1:0]
MS Byte
OC i HR
).
LS Byte
OC i LR
Table 22
– A timer interrupt is generated if the OCIE bit is
Clearing the output compare interrupt request is
done by:
3. Reading the SR register while the OCF i bit is
4. An access (read or write) to the OC i LR register.
Note: After a processor write cycle to the OC i HR
register, the output compare function is inhibited
until the OC i LR register is also written.
If the OC i E bit is not set, the OCMP i pin is a gen-
eral I/O port and the OLVL i bit will not appear
when match is found but an interrupt could be gen-
erated if the OCIE bit is set.
The value in the 16-bit OC
OLVL i bit should be changed after each success-
ful comparison in order to control an output wave-
form or establish a new elapsed timeout.
The OC
ing application can be calculated using the follow-
ing formula:
Where:
INTCLK
CC1-CC0 = Timer clock prescaler
The following procedure is recommended to pre-
vent the OCF i bit from being set between the time
it is read and the write to the OC
– Write to the OC i HR register (further compares
– Read the SR register (first step of the clearance
– Write to the OC i LR register (enables the output
t
set in the CR2 register and OCIS bit (or EFTIS bit
if only global interrupt is available) is set in the
CR3 register.
are inhibited).
of the OCF i bit, which may be already set).
compare function and clears the OCF i bit).
set.
i
R register value required for a specific tim-
= Desired output compare period (in
= Internal clock frequency
seconds)
OC i R =
(CC1.CC0)
t
*
i
R register and the
INTCLK
i
R register: