VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 34

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

3.13
3.13.1
3.13.2
Revision 4.3
August 2009
LED Pulsing Enable To provide additional power savings, the LEDs (when asserted)
can be pulsed at 5 kHz, 20% duty cycle.
Testing Features
The VSC8641 device includes several testing features designed to make it easier to
perform system-level debugging and in-system production testing. This section
describes the available features.
Ethernet Packet Generator (EPG)
The device EPG can be used at each of the 10/100/1000BASE-T speed settings to
isolate problems between the MAC and the VSC8641 device, or between a locally
connected PHY and its remote link partner. Enabling the EPG feature effectively disables
all MAC interface transmit pins and selects the EPG as the source for all data
transmitted onto the twisted pair interface.
Note The EPG is intended for use with laboratory or in-system testing equipment only.
Do not use the EPG testing feature when the VSC8641 device is connected to a live
network.
To enable the VSC8641 device EPG feature, set the device register bit 29E.15 to 1.
When the EPG is enabled, packet loss occurs during transmission of packets from the
MAC to the PHY. However, the PHY receive output pins to the MAC are still active when
the EPG is enabled. If it is necessary to disable the MAC receive pins as well, set
register bit 0.10 to 1.
When the device register bit 29E.14 is set to 1, the PHY begins transmitting Ethernet
packets based on the settings in registers 29E and 30E. These registers set:
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If register bit 29E.13 is set to 0, register bit 29E.14 is cleared automatically after
30,000,000 packets are transmitted.
CRC Counters
Two separate cyclical redundancy checking (CRC) counters are available in the
VSC8641 device. There is a 14-bit CRC good counter available in register bits 18E.13:0
and a separate 8-bit CRC error counter available in register bits 23E.7:0.
The device CRC counters operate in 10/100/1000BASE-T testing as follows:
Source and destination addresses for each packet
Packet size
Inter-packet gap
FCS state
Transmit duration
Payload pattern
Functional Descriptions
VSC8641 Datasheet
Page 34