MT46H8M32LFB5-6:A Micron Technology Inc, MT46H8M32LFB5-6:A Datasheet - Page 34
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MT46H8M32LFB5-6:A
Manufacturer Part Number
MT46H8M32LFB5-6:A
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H8M32LFB5-6A.pdf
(96 pages)
Specifications of MT46H8M32LFB5-6:A
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
6.5/5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
120mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46H8M32LFB5-6:A
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT46H8M32LFB5-6:A TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
DESELECT
NO OPERATION
LOAD MODE REGISTER
ACTIVE
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Notes:
Table 14: DM Operation Truth Table
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the device. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to instruct the selected device to perform
a NOP. This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
The mode registers are loaded via inputs A[0:n]. See mode register descriptions in Stand-
ard Mode Register (page 49) and Extended Mode Register (page 53). The LOAD
MODE REGISTER command can only be issued when all banks are idle, and a subse-
quent executable command cannot be issued until
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The values on the BA0 and BA1 inputs select the bank, and the address provided
on inputs A[0:n] selects the row. This row remains active for accesses until a PRE-
CHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
Name (Function)
Write enable
Write inhibit
1. Used to mask write data; provided coincident with the corresponding data.
2. All states and sequences not shown are reserved and/or illegal.
34
256Mb: x16, x32 Mobile LPDDR SDRAM
DM
H
L
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
MRD is met.
Valid
DQ
X
©2008 Micron Technology, Inc. All rights reserved.
Commands
Notes
1, 2
1, 2