MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 299

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV field.
Freescale Semiconductor
Reset
FDIVLCK
FDIV[5:0]
FDIVLD
W
R
Field
5–0
7
6
FDIVLD
Clock Divider Loaded
Clock Divider Locked
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash
program and erase algorithms.
refer to
7
0
The FCLKDIV register must never be written to while a Flash command is executing
(CCIF=0). The FCLKDIV register is writable during the Flash reset sequence even though
CCIF is clear.
0
1
0
1
writability to the FDIV field.
Section 4.40.4.3, “Flash Command Operations,”
FCLKDIV register has not been written since the last reset
FCLKDIV register has been written since the last reset
FDIV field is open for writing
FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore
FDIVLCK
6
0
= Unimplemented or Reserved
Table 408. Flash Clock Divider Register (FCLKDIV)
Table 409. FCLKDIV Field Descriptions
Table 410
MM912_634 Advance Information, Rev. 4.0
5
0
shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please
CAUTION
4
0
Description
for more information.
3
0
FDIV[5:0]
2
0
1
0
0
0
299