MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 219

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor
breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed.
4.32.4.5
The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a
circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide
word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next
read receives fresh information. Data is stored in the format shown in
DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer whilst the DBG is
armed returns invalid data and the trace buffer pointer is not incremented.
4.32.4.5.1
Using the TALIGN bit (see
the end or the beginning of a tracing session.
If end alignment is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State
signals the end of the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. Using end alignment or when
the tracing is initiated by writing to the TRIG bit whilst configured for begin alignment, tracing starts in the second cycle after the
DBGC1 write cycle.
4.32.4.5.1.1
Storing with begin alignment, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is
met the DBG module remains armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the
change-of-flow instruction the change of flow associated with the trigger is stored in the Trace Buffer. Using begin alignment
together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing
session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.
4.32.4.5.1.2
Storing with end alignment, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module
becomes disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction, the trigger event is
not stored in the Trace Buffer. If all trace buffer lines have been used before a trigger event occurs then the trace continues at
the first line, overwriting the oldest entries.
4.32.4.5.2
Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using
the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections.
4.32.4.5.2.1
In Normal Mode, change of flow (COF) program counter (PC) addresses are stored.
COF addresses are defined as follows:
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are
not stored in the trace buffer.
Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate
whether the stored address was a source address or destination address.
Freescale Semiconductor
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Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
Destination address of indexed JMP, JSR, and CALL instruction
Destination address of RTI, RTS, and RTC instructions
Vector address of interrupts, except for BDM vectors
Trace Buffer Operation
Trace Trigger Alignment
Storing with Begin Trigger Alignment
Storing with End Trigger Alignment
Trace Modes
Normal Mode
When a COF instruction with destination address is executed, the destination address is
stored to the trace buffer on instruction completion, indicating the COF has taken place. If
an interrupt occurs simultaneously then the next instruction carried out is actually from the
interrupt service routine. The instruction at the destination address of the original program
flow gets executed after the interrupt service routine.
Section 4.32.3.2.3, “Debug Trace Control Register
MM912_634 Advance Information, Rev. 4.0
NOTE
Table 324
(DBGTCR)) it is possible to align the trigger with
and
Table
. After each store the counter register
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