MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 156

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.27.8.3
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
4.27.8.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the Flash memory. If double
faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in
more detail in the Flash module
4.27.8.3.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being
programmed or the sector/block being erased is not guaranteed.
4.27.8.3.3
Refer to the PIM section for reset configurations of all peripheral module ports.
4.27.8.3.4
The RAM arrays are not initialized out of reset.
4.27.9
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are loaded from the Flash
register FOPT. See
global address 0x3_FF0E during the reset sequence.
Freescale Semiconductor
Note:
144.
Vector Address
Vector base + $80
16 bits vector address based
COP Configuration
Effects of Reset
Flash Configuration Reset Sequence Phase
Reset While Flash Command Active
I/O Pins
Memory
(144)
Table 226
and
NV[2:0] in FOPT Register
Section 4.40.6,
NV[3] in FOPT Register
Table 227
Table 225. Interrupt Vector Locations (Sheet 2 of 2)
Interrupt Source
Spurious interrupt
Table 226. Initial COP Rate Configuration
000
001
010
011
100
101
110
111
Table 227. Initial WCOP Configuration
1
0
MM912_634 Advance Information, Rev. 4.0
for coding. The FOPT register is loaded from the Flash configuration field byte at
“Initialization”.
CR[2:0] in COPCTL Register
WCOP in COPCTL Register
Mask
CCR
—
110
101
100
011
010
001
000
111
0
1
Local Enable
MM912_634 - MCU Die Overview
None
from STOP
Wake-up
-
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