MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 228

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

On simultaneous matches the lowest channel number has priority so with this configuration the forking from State1 has the
peculiar effect that a simultaneous match0/match1 transitions to final state but a simultaneous match2/match1transitions to
state2.
4.32.5.9
Trigger when a routine/event at M2 follows either M1 or M0.
Trigger when an event M2 is followed by either event M0 or event M1
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding.
4.32.5.10
Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed again. This cannot be
realized with theS12SDBGV1 SCR encoding due to OR limitations. By changing the SCR2 encoding as shown in red this
scenario becomes possible.
4.32.5.11
Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1. As shown up to 2
consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs
following the second M2, before M1 resets to State1 then a trigger is generated. Configuring CompA and CompC the same, it is
possible to generate a breakpoint on the third consecutive occurrence of event M0 without a reset M1.
Freescale Semiconductor
Scenario 8
Scenario 9
Scenario 10
SCR1=1101
State1
SCR1=0111
State1
SCR1=0111
SCR1=0010
State1
State1
M1
MM912_634 Advance Information, Rev. 4.0
SCR2=1100
M01
M2
State2
M01
M0
M2
Figure 79. Scenario 8a
Figure 80. Scenario 8b
Figure 78. Scenario 7
Figure 81. Scenario 9
SCR2=1111
SCR2=0101
SCR2=0111
State2
State2
State2
M2
M02
SCR3=1101
M01
State3
M2
M01
Final State
M01
Final State
Final State
M12
Final State
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