MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 283

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.39.3.2.5
Read: Anytime; read data only valid when SPIF is set
Write: Anytime
The SPI data register is both the input and output register for SPI data. A write to this register allows data to be queued and
transmitted. For an SPI configured as a master, queued data is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept
new data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and data has been received, the received data is transferred from the receive shift register to the SPIDR and
SPIF is set.
If SPIF is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the
receive shift register until the start of another transmission. The data in the SPIDR does not change.
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of a third transmission, the data
in the receive shift register is transferred into the SPIDR and SPIF remains set (see
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in
the receive shift register has become invalid and is not transferred into the SPIDR (see
Freescale Semiconductor
Reset
Reset
W
W
R
R
Receive Shift Register
SPI Data Register
R15
T15
R7
T7
7
0
7
0
SPI Data Register (SPIDR = SPIDRH:SPIDRL)
SPIF
Data A Received
R14
T14
R6
T6
6
0
6
0
= Unspecified
Figure 105. Reception with SPIF Serviced in Time
Table 401. SPI Data Register High (SPIDRH)
Table 402. SPI Data Register Low (SPIDRL)
Data A
MM912_634 Advance Information, Rev. 4.0
R13
T13
R5
T5
5
0
5
0
Data A
R12
T12
R4
T4
4
0
4
0
= Reception in progress
Data B Received
R11
T11
R3
T3
3
0
3
0
Data B
Figure
SPIF Serviced
Figure
R10
T10
R2
T2
Data B
2
0
2
0
105).
106).
Data C Received
R9
T9
R1
T1
1
0
1
0
Data C
Data C
R8
R0
T8
T0
0
0
0
0
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