PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 45

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

2.2
The SCOUT supports the IOM-2 interface in terminal mode with single clock and double
clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge
of FSC indicates the start of an IOM-2 frame. The FSC signal is generated by the receive
DPLL which synchronizes to the received line frame. The DCL and the BCL output clock
signals synchronize the data transfer on both data lines. The DCL is twice the bit rate,
the BCL output rate is equal to the bit rate. The bits are shifted out with the rising edge
of the first DCL clock cycle and sampled at the falling edge of the second clock cycle.
The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be
used to connect time slot oriented standard devices to the IOM-2 interface.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register. The BCL clock output can be enabled separately with the EN_BCL bit.
The clock rate or frequency respectively of the IOM-signals in TE mode are:
DD, DU: 768 kbit/s
DCL: 1536 kHz (double clock rate); 768 kHz (single clock rate if DIS_TR = ’1’)
FSC: 8 kHz.
If the transceiver is disabled (TR_CONF.DIS_TR) the DCL and FSC pins become input
and the HDLC and codec parts can still work via IOM-2. In this case it can be selected
with the clock mode bit (IOM_CR.CLKM) between a double clock and a single clock
input.
Note: One IOM-2 frame has to consist of a multiple of 64 (32) DCL clocks for a double
Figure 19
Clock waveforms
Data Sheet
(single) clock selection.
IOM-2 Interface
FSC
DCL
BCL
35
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12