PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 107

• Manufacturer Part Number: PSB21383HV13XT
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3
The HDLC controller handles layer-2 functions of the D- channel protocol (LAPD) or B-
channel protocols. It can access the D or B-channels or any combination of them e.g. 18
bit IDSL data (2B+D) by setting the enable HDLC channel bits (EN_D, EN_B1H,
EN_B2H) in the HCI_CR register.
It performs the framing functions used in HDLC based communication: flag generation/
recognition, bit stuffing, CRC check and address recognition.
One 64 byte FIFO for the receive and one for the transmit direction are available. They
are implemented as cyclic buffers. The transceiver reads and writes data sequentially
with constant data rate whereas the data transfer between FIFO and microcontroller
uses a block oriented protocol with variable block sizes.
The configuration, control and status bits related to the HDLC controller are all assigned
to the address range 20
3.1
The HDLC controller can be programmed to operate in various modes, which are
different in the treatment of the HDLC frame in receive direction. Thus the receive data
flow and the address recognition features can be programmed in a flexible way to satisfy
different system requirements.
The structure of a LAPD two-byte address is shown below.
For the address recognition the HDLC controller contains four programmable registers
for individual SAPI and TEI values (SAP1, 2 and TEI1, 2), plus two fixed values for the
“group” SAPI (SAPG = ’FE’ or ’FC’) and TEI (TEIG = ’FF’).
The received C/R bit is excluded from the address comparison. EA is the address field
extension bit which is set to ’1’ for LAPD protocol.
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODEH register:
Data Sheet
SAPI1, 2, SAPG
High Address Byte
HDLC Controller
Message Transfer Modes
H
-29
H
C/R 0
. (see chapter 7.1).
97
TEI 1, 2, TEIG
Low Address Byte
HDLC Controller
EA
PSB 21381/2
PSB 21383/4
2001-03-12