PSB21383HV13XT Infineon Technologies, PSB21383HV13XT Datasheet - Page 133

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PSB21383HV13XT

Manufacturer Part Number
PSB21383HV13XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21383HV13XT

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
The GR-gain adjustment stage is digitally programmable from – 6 to 0 dB in steps
CRAM to set GR to the desired value. After reset, the GR-gain stage is bypassed.
A low-pass filter limits the signal bandwidth in the receive direction according to ITU-T
and ETSI (NET33) recommendations.
A series of low-pass interpolation filters increases the sampling frequency up to the
desired value. The last interpolator feeds the D/A-converter.
Figure 74
Architecture of the FX- and FR-Correction Filter
Data Sheet
0.25 dB (–
dB and others are also possible). Respectively two bytes are coded in the
Equalizer 1
Equalizer 2
123
High- / Low- Pass
PSB 21381/2
PSB 21383/4
ITD02288
2001-03-12
Codec

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