PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 236

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

TMB
4.6.14
Value after reset: 00
TLP ... Test Loop
The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming
from the layer 1 controller will not be forwarded to the layer 2 controller.
4.6.15
RFIFOB
A read access to this register gives access to the “current” FIFO location selected by an
internal pointer which is automatically incremented after each read access.
The RFIFOB contains up to 128 bytes of received data.
After an ISTAB.RPF interrupt, a complete data block is available. The block size can be
8, 16, 32 or 64 bytes depending on the EXMB.RFBS setting.
After an ISTAB.RME interrupt, the number of received bytes can be obtained by reading
the RBCLB register.
4.6.16
XFIFOB
A write access to this register gives access to the “current” FIFO location selected by an
internal pointer which is automatically incremented after each write access.
Depending on EXMB.XFBS up to 32 or 64 bytes of transmit data can be written to the
XFIFOB following an ISTAB.XPR interrupt.
Data Sheet
7
7
7
TMB -Test Mode Register B-Channels
RFIFOB - Receive FIFO B-Channels
XFIFOB - Transmit FIFO B-Channels
0
H
0
0
Transmit data
Receive data
0
236
0
0
Detailed Register Description
0
0
0
0
TLP
PSB/PSF 21150
WR (7A/8A)
RD (7A/8A)
2003-01-30
IPAC-X
RD/WR
(79/89)