PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 159

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.9.3.2
The transmission of transparent frames (XTF command) is shown in
For transparent frames, the whole frame including address and control field must be
written to the XFIFOx. The host configures whether the CRC is generated and appended
to the frame (default) or not (selected in EXMx.XCRC).
Further, the host selects the interframe time fill signal which is transmitted between
HDCL frames (EXMx.ITF). One option is to send continuous flags (’01111110’), however
if D-channel access handling (collision resolution on the S bus) is required, the signal
must be set to idle (continuous ’1’s are transmitted). Reprogramming of ITF takes effect
only after the transmission of the current frame has been completed or after an XRES
command.
Figure 85
3.9.4
By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) in the DCI_CR register
(D-channel) and in the BCH_CR register (B-channel) the HDLC controller can access
the D, B1 and B2 channels or any combination of them (e.g. 18 bit IDSL data 2B+D). In
all modes (except extended transparent mode) transmission always works frame
aligned, i.e. it starts with the first selected channel, whereas reception searches for a flag
anywhere in the serial data stream.
3.9.5
This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent
mode fully transparent data transmission/reception without HDLC framing is performed
i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism.
This allows user specific protocol variations.
Data Sheet
Transmit Transparent Frame
*
1)
Transmit Frame Structure
Access to IOM-2 channels
Extended Transparent Mode
The CRC is generated by default.
If EXMR.XCRC is set no CRC is appended
Transmit Data Flow
(XTF)
FLAG
ADDRESS
ADDR
159
XFIFO
CONTROL
CTRL
Description of Functional Blocks
I
DATA
CHECKRAM
CRC
*
1)
PSB/PSF 21150
Figure
fifoflow_tran.vsd
FLAG
85.
2003-01-30
IPAC-X