PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 184

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

TMD
MDS2-0
010
(Non-Auto/8
Mode)
011
(Non-Auto/16
Mode)
111
(Transparent
Mode1)
101
(Transparent
Mode 2)
Note: If SAP1 and SAP2 contain identical values, the combination SAP1,2-TEIG will
C/R ... Command/Response
The C/R bit contains the C/R bit of the received frame (Bit1 in the SAPI address)
Note: The contents of RSTAD corresponds to the last received HDLC frame; it is
4.1.17
Value after reset: 00
For general information please refer to
Data Sheet
only be indicated by SA1,0 = ’10’ (i.e. the value ’00’ will not occur in this case).
duplicated into RFIFOD for every frame (last byte of frame)
7
TMD -Test Mode Register D-Channel
0
SA1
x
x
0
0
0
0
1
1
0
0
1
-
-
1
H
0
0
SA0
x
x
0
0
1
1
0
0
0
1
0
-
-
1
0
Chapter
184
TA
0
1
0
1
0
1
0
1
x
x
x
0
1
x
0
3.10.
0
Detailed Register Description
1
TEI2
TEI1
SAP2
SAP2
SAPG
SAPG
SAP1
SAP1
SAP2
SAPG
SAP1
-
-
st
Byte
0
Address Match with
0
TLP
reserved
PSB/PSF 21150
2
-
-
TEIG
TEI2
TEIG
TEI1 or TEI2
TEIG
TEI1
-
-
-
TEIG
TEI1 or TEI2
nd
RD/WR (29)
Byte
2003-01-30
IPAC-X