PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 97

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Figure 55
When the TIC bus is seized by the ISAC-SX TE, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the ISAC-SX TE is automatically set into a
lower priority class, that is, a new bus access cannot be performed until the status "bus
free" is indicated in two successive frames.
If none of the devices connected to the IOM-2 interface request access to the D and C/
I channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the
3.7.5.2
The S-bus access procedure specified in ITU I.430 was defined to organize D-channel
access with multiple TEs connected to a single S-bus
To implement collision detection the D (channel) and E (echo) bits are used. The
D-channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit, i.e.
the availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the
DD last octet of Ch2 channel
S/G = 1 : stop
S/G = 0 : go
Data Sheet
DU
is no more requested, to grant other devices access to the D and C/I channels.
S-Bus Priority Mechanism for D-Channel
Structure of Last Octet of Ch2 on DU
(Figure
56).
97
Description of Functional Blocks
m
P when access to the C/I channels
(Figure
57).
ISAC-SX TE
PSB 3186
2003-01-30