PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 14

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

IOM-2
IOM-2 Interface
Monitor channel
programming
C/I channels
Layer 1 state machine
Layer 1 state machine
in software
HDLC support
D-channel FIFO size
Reset Signals
Reset Sources
Interrupt Output Signals
Pin SCLK
Data Sheet
ISAC-SX TE PSB 3186
Double clock (DCL),
bit clock pin (BCL),
serial data strobe (SDS)
Provided
(MON0, 1, 2, ..., 7)
CI0 (4 bit),
CI1 (4/6 bit)
With changes for
correspondence with the
actual ITU specification
Not possible
D- and B-channel timeslots;
non-auto mode,
transparent mode 1-3,
extended transparent mode
64 bytes cyclic buffer per
direction with programmable
FIFO thresholds
RES input signal
RSTO output signal
RES Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
INT
low active (open drain) by
default, reprogrammable to
high active (push-pull)
1.536 MHz
14
ISAC-S TE PSB 2186
Double clock (DCL),
bit clock (BCL),
serial data strobe (SDS)
Provided
(MON0 or 1)
CI0 (4 bit),
CI1 (6 bit)
Not possible
D-channel timeslot;
auto mode,
non-auto mode,
transparent mode 1-3
2x32 bytes buffer per
direction
RST input/output signal
RST Input
Watchdog
C/I Code Change
EAW Pin
Low active INT
512 kHz
ISAC-SX TE
PSB 3186
2003-01-30
Overview