PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 78

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy)
overflow interrupts (STOVxy)
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected timeslot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
An STOVxy
acknowledged. However, if STIxy
STIxy
Table 10
generated because an STI interrupt was not acknowledged before.
In example 1 only the STIxy
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy
disabled. STIxy
generated due to STIxy
enabled, so STOVxy
In example 5 additionally the STIxy
generated due to STIxy
Compared to the previous example STOVxy
not generated and STOVxy
Compared to example 5 in example 7 a third STOVxy
generated additionally for both STIxy
1)
2)
Data Sheet
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
1
which is enabled and not acknowledged.
gives some examples for that. It is assumed that an STOV interrupt is only
0
is related to its STIxy
1
is disabled but its STOVxy
0
0
and STOVxy
is enabled and generated and the corresponding STOVxy
0
0
and STOVxy
. In example 4 additionally the corresponding STOVxy
1
0
2)
is only generated for STIxy
is enabled and thus STIxy
in the STI register.
0
0
1
is masked, the STOVxy
and is only generated if STIxy
1
are both generated due to STIxy
0
1
is enabled with the result that STOVxy
and STIxy
is only generated due to STIxy
0
78
and xy
0
1
is disabled in example 6, so STOVxy
is enabled, and therefore STOVxy
1
.
1
Description of Functional Blocks
are used to refer to two different
2
is enabled and thus STOVxy2 is
0
1
is only generated. If no STI is
but not for STIxy
1)
0
is generated for any other
and synchronous transfer
0
is enabled and not
0
1
.
.
ISAC-SX TE
0
.
PSB 3186
2003-01-30
0
is only
0
0
1
0
is
is
is
is