PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 55

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Note: i = input; o = output;
3.4.1
The receive PLL performs phase tracking between the F/L transition of the receive signal
and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1
XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to
generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output is set to a specific phase relationship, thus causing once an irregular FSC timing.
The phase relationships of the clocks are shown in
Figure 29
3.4.2
The timing extraction jitter of the ISAC-SX TE conforms to ITU-T Recommendation I.430
(– 7% to + 7% of the S-interface bit period).
Data Sheet
FSC
7.68 MHz
1536 kHz *
768 kHz
1) The S transceiver can be disabled (TR_CONF0.DIS_TR=1) so the IOM clocks
become inputs and with IOM_CR.CLKM the DCL input can be selected to double
clock (0) or single bit clock (1).
2) The direction input/output refers to the direction of the B- and D-channel data
stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the
direction of some other timeslots may be different if this is programmed by the host
(e.g. for data exchange between different devices connected to IOM-2).
Description of the Receive PLL (DPLL)
Jitter
F-bit
Phase Relationships of ISAC-SX TE Clock Signals
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
55
Figure
Description of Functional Blocks
29.
ISAC-SX TE
PSB 3186
2003-01-30
ITD09664