PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 68

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3.7
The ISAC-SX TE supports the IOM-2 interface in terminal mode with single clock and
double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. Another
clock signal BCL provides a single bit clock. The rising edge of FSC indicates the start
of an IOM-2 frame. The DCL and the BCL clock signals synchronize the data transfer on
both data lines DU and DD. The DCL is twice the bit rate, the BCL rate is equal to the bit
rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled
at the falling edge of the second clock cycle.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
The IOM clock signals are generated by the receive DPLL which synchronizes the FSC
to the received S/T frame.
The BCL clock together with the serial data strobe signals SDS can be used to connect
timeslot oriented standard devices to the IOM-2 interface. If the transceiver is disabled
(TR_CON.DIS_TR) the DCL and FSC pins become input and the HDLC part can still
work via IOM-2. In this case the clock mode bit (IOM_CR.CLKM) selects between a
double clock and a single clock input for DCL.
The clock rate/frequency of the IOM-2 signals in TE mode are:
DD, DU: 768 kbit/s
FSC (o): 8 kHz
DCL (o): 1536 kHz (double clock rate)
BCL (o): 768 kHz (single clock rate)
Option - Transceiver disabled (DIS_TR = ’1’):
FSC (i):
DCL (i):
Data Sheet
8 kHz
1536 ... 4096 kHz, in steps of 512 kHz (double clock rate)
IOM-2 Interface
68
Description of Functional Blocks
ISAC-SX TE
PSB 3186
2003-01-30