STM32W108CBU64TR STMicroelectronics, STM32W108CBU64TR Datasheet - Page 87

• Manufacturer Part Number: STM32W108CBU64TR
• Description: MCU, RF, 32BIT, 128K FLASH, 48VFQFPN
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU64TR

• Controller Family/series: STM32
• Core Size: 32bit
• No. Of I/o's: 24
• Program Memory Size: 128KB
• Ram Memory Size: 8KB
• Cpu Speed: 24MHz
• Oscillator Type: Internal, External
• No. Of Timers: 2
• Rohs Compliant: Yes
• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
Table 22.
1. The notation xxx means that the corresponding column header below is inserted to form the field name.
9.6.4
FLOW
0
1
1
SC1_UARTxxx
SC1_UARTCFG
AUTO
0
1
-
Figure 13. RTS/CTS flow control connections
The UART RTS/CTS flow control options are selected by the SC1_UARTFLOW and
SC1_UARTAUTO bits in the SC1_UARTCFG register (see
SC1_UARTFLOW bit is set, the UART will not start transmitting a character unless nCTS is
low (asserted). If nCTS transitions to the high state (deasserts) while a character is being
transmitted, transmission of that character continues until it is complete.
If the SC1_UARTAUTO bit is set, nRTS is controlled automatically by hardware: nRTS is put
into the low state (asserted) when the receive FIFO has room for at least two characters,
otherwise is it in the high state (unasserted). If SC1_UARTAUTO is clear, software controls
the nRTS output by setting or clearing the SC1_UARTRTS bit int the SC1_UARTCFG
register. Software control of nRTS is useful if the external serial device cannot stop
transmitting characters promptly when nRTS is set to the high state (deasserted).
UART RTS/CTS flow control configurations
DMA
The DMA Channels section describes how to configure and use the serial receive and
transmit DMA channels.
The receive DMA channel has special provisions to record UART receive errors. When the
DMA channel transfers a character from the receive FIFO to a buffer in memory, it checks
the stored parity and frame error status flags. When an error is flagged, the
SC1_RXERRA/B register is updated, marking the offset to the first received character with a
parity or frame error. Similarly if a receive overrun error occurs, the SC1_RXERRA/B
registers mark the error offset. The receive FIFO hardware generates the INT_SCRXOVF
interrupt and DMA status register indicates the error immediately, but in this case the error
(1)
RTS
0/1
-
-
nCTS, nRTS
nCTS, nRTS
TXD, RXD,
TXD, RXD,
Pins used
TXD, RXD
UART Transmitter
UART Receiver
STM32W108
No RTS/CTS flow control
Flow control using RTS/CTS with software control of nRTS:
nRTS controlled by SC1_UARTRTS bit in SC1_UARTCFG register
Flow control using RTS/CTS with hardware control of nRTS:
nRTS is asserted if room for at least 2 characters in receive FIFO
Doc ID 16252 Rev 8
RXD
nRTS
TXD
nCTS
Operating mode
nCTS
nRTS
RXD
TXD
Table
UART Transmitter
UART Receiver
Other Device
22). Whenever the
Serial interfaces
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