STM32W108CBU64TR STMicroelectronics, STM32W108CBU64TR Datasheet - Page 81

• Manufacturer Part Number: STM32W108CBU64TR
• Description: MCU, RF, 32BIT, 128K FLASH, 48VFQFPN
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU64TR

• Controller Family/series: STM32
• Core Size: 32bit
• No. Of I/o's: 24
• Program Memory Size: 128KB
• Ram Memory Size: 8KB
• Cpu Speed: 24MHz
• Oscillator Type: Internal, External
• No. Of Timers: 2
• Rohs Compliant: Yes
• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
9.5.1
Note:
9.5.2
The I
●
●
Table 17
pins are configured as open-drain outputs, they require external pull-up resistors.
Table 17.
Setup and configuration
The I
operates only in master mode and supports both Standard (100 kbps) and Fast (400 kbps)
I
supported.
The I
generator. SCL is produced by dividing down 12 MHz according to this equation:
EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the
SCx_RATELIN register.
Standard-Mode I
Table 18.
At 400 kbps, the Philips I
1.3 µs, but on the STM32W108 it is 1.25 µs. If a slave device requires strict compliance with
SCL timing, the clock rate must be lowered to 375 kbps.
Constructing frames
The I
SC_TWISTART, SC_TWISTOP, SC_TWISEND, and SC_TWIRECV bits in the
SCx_TWICTRL1 registers.
2
Direction
GPIO configuration
SC1 pin
SC2 pin
C modes. Address arbitration is not implemented, so multiple master applications are not
SDA (Serial Data) - bidirectional serial data
SCL (Serial Clock) - bidirectional serial clock
2
2
2
2
C master controller uses just two signals:
C controller is enabled by writing 3 to the SCx_MODE register. The I
C master controller's serial clock (SCL) is produced by a programmable clock
C master controller supports generating various frame segments by means of the
lists the GPIO pins used by the SC1 and SC2 I
Parameter
Clock rate
100 kbps
375 kbps
400 kbps
I
I
2
2
C Master GPIO Usage
C clock rate programming
2
C (100 kbps) and Fast-Mode I
I2C clock rate programming on page 81
2
C Bus specification requires the minimum low period of SCL to be
Figure 19
Doc ID 16252 Rev 8
Rate
summarizes these frames.
Alternate Output
=
SCx_RATELIN
Input / Output
(open drain)
---------------------------------------- -
(
LIN
SDA
PB1
PA1
14
15
14
12MHz
+
2
C (400 kbps) operation.
1
)x2
2
EXP
C master controllers. Because the
shows the rate settings for
Alternate Output
SCx_RATEEXP
Input / Output
(open drain)
Serial interfaces
SCL
PB2
PA2
2
C controller
3
1
1
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