IDT82P2282PFG IDT, Integrated Device Technology Inc, IDT82P2282PFG Datasheet - Page 169

• Manufacturer Part Number: IDT82P2282PFG
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PFG

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82P2282PFG

T1/J1 FRMR Interrupt Indication 1 (053H, 153H)
RMFBI:
SFEI:
When 2 or more Ft bit errors are detected in a 6-basic-frame fixed window, the severely Ft bit error occurs
occurs.
When 2 or more Ft bit errors are detected in a 6-basic-frame fixed window, the severely Ft bit error occurs.
BEEI:
frame, a single CRC-6 error event is generated
FERI:
alignment bit error event.
Table 15). Each unmatched bit leads to a F-bit error event.
Programming Information
IDT82P2282
Bit Name
Default
Bit No.
Type
= 0: The received bit is not the first bit of each SF/ESF/T1 DM/SLC-96 frame.
= 1: The first bit of each SF/ESF/T1 DM/SLC-96 frame is received.
This bit will be cleared if a ’1’ is written to it. This bit can not be updated during out of synchronization state.
In SF format, each received Ft bit is compared with the expected one (refer to Table 12). Each unmatched Ft bit leads to an Ft bit error event.
= 0: No Severely Ft Bit Error event is detected.
= 1: The Severely Ft Bit Error event is detected.
In ESF format, when 2 or more frame alignment bit errors are detected in a 1-ESF-frame fixed window, the severely frame alignment bit error
= 0: No Severely Frame Alignment Bit Error event is detected.
= 1: The Severely Frame Alignment Bit Error event is detected.
In T1 DM format, each received Ft bit is compared with the expected one (refer to Table 14). Each unmatched Ft bit leads to an Ft bit error event.
= 0: No Severely Ft Bit Error event is detected.
= 1: The Severely Ft Bit Error event is detected.
This bit will be cleared if a ’1’ is written to it.
In ESF format, when the local calculated CRC-6 of the current received ESF frame does not match the received CRC-6 of the next received ESF
= 0: No CRC-6 Error event is detected.
= 1: The CRC-6 Error event is detected.
This bit will be cleared if a ’1’ is written to it.
In SF format, each received F bit is compared with the expected one (refer to Table 12). Each unmatched F bit leads to an F bit error event.
= 0: No F Bit Error event is detected.
= 1: The F Bit Error event is detected.
In ESF format, each received Frame Alignment bit is compared with the expected one (refer to Table 13). Each unmatched bit leads to a frame
= 0: No Frame Alignment Bit Error event is detected.
= 1: The Frame Alignment Bit Error event is detected.
In T1 DM format, each received F bit is compared with the expected one (refer to Table 14). Each unmatched F bit leads to an F bit error event
= 0: No F Bit Error event is detected.
= 1: The F Bit Error event is detected.
In SLC-96 format, The Ft bit in each odd frame and the Fs bit in Frame (2n) (0<n<12 and n=36) is compared with the expected one (refer to
= 0: No F Bit Error event is detected.
= 1: The F Bit Error event is detected.
This bit will be cleared if a ’1’ is written to it.
7
Reserved
6
5
RMFBI
R
4
0
169
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
SFEI
R
3
0
BEEI
R
2
0
FERI
R
1
0
August 20, 2009
COFAI
R
0
0