IDT82P2282PFG IDT, Integrated Device Technology Inc, IDT82P2282PFG Datasheet - Page 138

• Manufacturer Part Number: IDT82P2282PFG
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PFG

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82P2282PFG

T1/J1 Transmit Configuration 4 (026H, 126H)
WDAT[6:0]:
SAMP[3:0] bits (b3~0, T1/J1-025H,...).
T1/J1 Receive Jitter Attenuation Configuration (027H, 127H)
RJITT_TEST:
current interval between the read and write pointer of the FIFO will be written into the RJITT[6:0] bits (b6~0, T1/J1-039H,...).
current interval is compared with the old one in the RJITT[6:0] bits (b6~0, T1/J1-039H,...) and the larger one will be indicated by the RJITT[6:0] bits
(b6~0, T1/J1-039H,...); otherwise, the value in the RJITT[6:0] bits (b6~0, T1/J1-039H,...) will not be changed.
RJA_LIMT:
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or wid-
ened.
bits window.
RJA_E:
RJA_DP[1:0]:
RJA_BW:
Programming Information
IDT82P2282
Bit Name
Bit Name
Default
Bit No.
Default
Bit No.
Type
These bits contain the data to be stored in the pulse template RAM which is addressed by the UI[1:0] bits (b5~4, T1/J1-025H,...) and the
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, T1/J1-039H,...). That is, the
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, T1/J1-039H,...). That is, the
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4
= 0: Disable the Receive Jitter Attenuator.
= 1: Enable the Receive Jitter Attenuator.
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
This bit select the Jitter Transfer Function Bandwidth.
= 0: 5 Hz.
= 1: 1.26 Hz.
Type
Reserved
7
7
Reserved
WDAT6
R/W
6
0
6
WDAT5
RJITT_TEST
R/W
5
0
R/W
5
0
WDAT4
R/W
RJA_LIMT
4
0
138
R/W
4
0
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
WDAT3
R/W
3
0
RJA_E
R/W
3
0
WDAT2
RJA_DP1
R/W
2
0
R/W
2
0
WDAT1
RJA_DP0
R/W
1
0
R/W
1
0
August 20, 2009
RJA_BW
WDAT0
R/W
R/W
0
0
0
0